DS90C3201VS National Semiconductor, DS90C3201VS Datasheet
DS90C3201VS
Specifications of DS90C3201VS
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DS90C3201VS Summary of contents
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... LVTTL data are transmitted at an effective rate of 945 Mbps per LVDS channel. Using a 135 MHz clock, the data through- put is 9.45Gbit/s (945Mbytes/s). This allows the dual 10-bit LVDS Transmitter to support HDTV resolutions. Block Diagram © 2008 National Semiconductor Corporation Features ■ 9.45Gbit/s data throughput ■ ...
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Typical Application Diagram Functional Description The DS90C3201 and DS90C3202 are a dual 10-bit color Transmitter and Receiver FPD-Link chipset designed to transmit data at clocks speeds from 8 to 135 MHz. DS90C3201 and DS90C3202 are designed to interface be- tween ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( LVCMOS/LVTTL Input −0. Voltage LVCMOS/LVTTL Output −0. Voltage LVDS Output Voltage −0. LVDS Short Circuit Duration Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 sec ...
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Symbol Parameter TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply Current Worst Case (Figures 2, 4) (Note 8) ICCTG Transmitter Supply Current Incremental Test Pattern (Figures 3, 4) (Note 9) ICCTZ Transmitter Supply Current Power Down Note 1: “Absolute Maximum Ratings” are ...
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Transmitter Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol LLHT LVDS Low-to-High Transition Time (Figure 5) LHLT LVDS High-to-Low Transition Time (Figure 5) TPPos1 Transmitter Output Pulse Position for bit 1 (1st bit) (Figure 13) ...
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Two-Wire Serial Communication Interface Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter f S2CLK Clock Frequency SC SC:LOW Clock Low Period SC:HIGH Clock High Period SCD:TR S2CLK and S2DAT Rise Time SCD:TF S2CLK and S2DAT Fall ...
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FIGURE 2. “Worst Case” Test Pattern FIGURE 3. Incremental Test Pattern FIGURE 4. Typical and Max ICC with Worst Case and Incremental Test Pattern 20147206 FIGURE 5. LVDS Transition Times 20147205 7 20147203 20147204 20147207 www.national.com ...
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FIGURE 7. Input Setup/Hold Time, High/Low Time, and Clock In to Clock Out Latency www.national.com FIGURE 6. Input Clock Transition Time FIGURE 8. Phase Lock Loop Set Time 8 20147208 20147209 20147210 ...
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FIGURE 9. Transmitter Powerdown Delay FIGURE 10. LVTLL Input Programmable Strobe Select FIGURE 11. Serializer Ideal Pulse Width 9 20147211 20147212 20147213 www.national.com ...
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User Programmable Internal Clock Delay Adjustment for Input Data Setup/Hold Optimization www.national.com Input Data Sampling Clock (TCLK IDS FIGURE 12. Input Data Sampling Clock 10 ) 20147214 ...
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FIGURE 13. LVDS Input Mapping and Ideal Transmitter Pulse Position 11 20147215 www.national.com ...
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Pin Diagram www.national.com DS90C3201 Transmitter 12 20147216 ...
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DS90C3201 Pin Descriptions Pin No. Pin Name 1 TXEC3 2 TXEC4 3 TXEC5 4 TXEC6 5 TXEB0 6 TXEB1 7 TXEB2 8 TXEB3 9 TXEB4 10 TXEB5 11 TXEB6 12 VDDE1 13 VSSE1 14 TXEA0 15 TXEA1 16 TXEA2 17 ...
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Pin No. Pin Name 44 TXEB - 45 TXEA+ 46 TXEA - 47 TCLKOUT+ 48 TCLKOUT - 49 VDDL 50 VSSL 51 TXOE+ 52 TXOE - 53 TXOD+ 54 TXOD - 55 TXOC+ 56 TXOC - 57 TXOB+ 58 TXOB ...
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Pin No. Pin Name 92 TXOB0 93 TXOB1 94 TXOB2 95 TXOB3 96 TXOB4 97 TXOB5 98 TXOB6 99 TXOA0 100 TXOA1 101 TXOA2 102 TXOA3 103 TXOA4 104 TXOA5 105 TXOA6 106 VDDT2 107 VDDT3 108 VSST2 109 VSST3 ...
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Two-Wire Serial Communication Interface Description The DS90C3201 operates as a slave on the Serial Bus, so the S2CLK line is an input (no clock is generated by the DS90C3201) and the S2DAT DS90C3201 has a fixed 7bit slave address. The ...
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DS90C3201 Two-Wire Serial Interface Register Table Address R/W RESET 0d/0h R PWDN 1d/1h R PWDN 2d/2h R PWDN 3d/3h R PWDN 4d/4h R PWDN 5d/5h R PWDN 6d/6h R PWDN 7d/7h R PWDN 8d/8h R PWDN 9d/9h R PWDN 10d/ah ...
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Address R/W RESET 28d/1ch R/W PWDN 29d/1dh R/W PWDN 30d/1eh R/W PWDN www.national.com Bit # Description [7] Vod adjustment for TCLK channel 0: TCLK Vod is the same as TXE EVEN BANK (Default) 1: TCLK Vod is the same as ...
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Address R/W RESET 31d/1fh R/W PWDN Bit # Description [7:6] 11: LVDS O/Ps available as long as "NO CLK" HIGH regardless PLL lock or not 10: LVDS O/Ps available after 1K of TCLK cycles detected & PLL generated ...
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... Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 128-Pin TQFP Package Order Number DS90C3201VS NS Package Number VJX128A 20 ...
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Notes 21 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock Conditioners www.national.com/timing Data Converters www.national.com/adc Displays www.national.com/displays Ethernet www.national.com/ethernet Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www ...