AT86RF211-DAI Atmel, AT86RF211-DAI Datasheet - Page 29

• Manufacturer Part Number: AT86RF211-DAI
• Manufacturer: Atmel

Specifications of AT86RF211-DAI

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Modulation Type: FSK
• Product Depth (mm): 7mm
• Product Length (mm): 7mm
• Operating Supply Voltage (typ): 2.5/3.3V
• Lead Free Status / Rohs Status: Not Compliant

Control Register (CTRL2)
Table 7. CTRL2 Overview
Register reset value = (00000057)
Table 8. CTRL2 Detailed Description
1942C–WIRE–06/02
DATARATE
Name
DATATOL
nbit
init
N0LD2
N1LD2
Name
LDCK
DATARATE
Number of
(0000)
31-18
bits
14
8
1
4
5
16
Received DATAMSG rate
Comments
This value must be programmed to have the DATACLK activated.
(selected with DATACLK bit in CTRL1 register).
Value from 1 kbps to 50 kbps
Tolerance for DATACLK, clock recovery
Recommended value = 2% of the rate.
Clock frequency is doubled to increase precision of PLL lock detection
0: 10 MHz clock frequency
1: doubled clock frequency
PLL unlock condition trigger
Recommended values are reset values
PLL lock condition trigger
Recommended values are reset values
16
•
The clock recovery function is activated by setting to ‘1’ the DATACLK bit of the CTRL1
register.
The clock recovery function provides on DATACLK pin the data clock, synchronized on
the received data flow. The targeted position for the rising edge of the clock is the mid-
dle of the data bit. It is then easy for the microcontroller to read without synchro troubles.
Clock recovery mechanism is based on the generation of a basic data clock with a
period given by DATARATE of CTRL2 with a step of about 100 ns. This basic clock is
synchronized on the received data flow with a phase correction step fixed by DATATOL
of CTRL2 register (step of about 100 ns also).
So, DATATOL can
The best value of DATATOL is a trade-off between these considerations. The typical
recommended value of RATETOL is 2% of DATARATE.
Clock Recovery Function
–
–
–
DATATOL
17-10
(00)
compensate for the difference between the read data rates from transmitter
and receiver (fixed by DATARATE).
allow fast initial synchronization of data clock, avoiding bit transition times
and converge toward the middle of the bit.
keep the right data rate (no additional and no removed bit) when a noisy
data with bad bit transition position arrives.
16
LDCK
9
0
N0LD1
(0010)
8-5
2
AT86RF211
reset value: (10111)
reset value: (0000)
reset value: (0010)
reset value: (00)
(10111)
N1LD2
reset value: 0
4-0
2
16
16
29
2
2