GAL22V10D-10LJ Lattice, GAL22V10D-10LJ Datasheet - Page 3
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GAL22V10D-10LJ
Manufacturer Part Number
GAL22V10D-10LJ
Description
SPLD - Simple Programmable Logic Devices 5V 22 I/O
Manufacturer
Lattice
Datasheet
1.GAL22V10D-10LJ.pdf
(23 pages)
Specifications of GAL22V10D-10LJ
Logic Family
GAL
Number Of Macrocells
10
Maximum Operating Frequency
125 MHz
Number Of Programmable I/os
10
Delay Time
10 ns
Operating Supply Voltage
5 V
Supply Current
130 mA
Maximum Operating Temperature
+ 75 C
Minimum Operating Temperature
0 C
Package / Case
PLCC-28
Mounting Style
SMD/SMT
Supply Voltage (max)
5.25 V
Supply Voltage (min)
4.75 V
Lead Free Status / Rohs Status
No
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• HIGH PERFORMANCE E
• ACTIVE PULL-UPS ON ALL PINS
• COMPATIBLE WITH STANDARD 22V10 DEVICES
• 50% to 75% REDUCTION IN POWER VERSUS BIPOLAR
• E
• TEN OUTPUT LOGIC MACROCELLS
• PRELOAD AND POWER-ON RESET OF REGISTERS
• APPLICATIONS INCLUDE:
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS
ESCRIPTION
The GAL22V10, at 4ns maximum propagation delay time, combines
a high performance CMOS process with Electrically Erasable (E
floating gate technology to provide the highest performance avail-
able of any 22V10 device on the market. CMOS circuitry allows
the GAL22V10 to consume much less power when compared to
bipolar 22V10 devices. E
erase times, providing the ability to reprogram or reconfigure the
device quickly and efficiently.
The generic architecture provides maximum design flexibility by
allowing the Output Logic Macrocell (OLMC) to be configured by
the user. The GAL22V10 is fully function/fuse map/parametric com-
patible with standard bipolar and CMOS 22V10 devices.
Unique test circuitry and reprogrammable cells allow complete AC,
DC, and functional testing during manufacture. As a result, Lat-
tice Semiconductor delivers 100% field programmability and func-
tionality of all GAL products. In addition, 100 erase/write cycles and
data retention in excess of 20 years are specified.
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
22v10_12
Features
Description
— 4 ns Maximum Propagation Delay
— Fmax = 250 MHz
— 3.5 ns Maximum from Clock Input to Data Output
— UltraMOS
— Fully Function/Fuse-Map/Parametric Compatible
— 90mA Typical Icc on Low Power Device
— 45mA Typical Icc on Quarter Power Device
— Reconfigurable Logic
— Reprogrammable Cells
— 100% Tested/100% Yields
— High Speed Electrical Erasure (<100ms)
— 20 Year Data Retention
— Maximum Flexibility for Complex Logic Designs
— 100% Functional Testability
— DMA Control
— State Machine Control
— High Speed Graphics Processing
— Standard Logic Speed Upgrade
2
CELL TECHNOLOGY
with Bipolar and UVCMOS 22V10 Devices
®
Advanced CMOS Technology
2
technology offers high speed (<100ms)
2
CMOS
®
TECHNOLOGY
2
)
1
Functional Block Diagram
Pin Configuration
NC
I
I
I
I
I
I
I/CLK
11
5
7
9
12
4
I
I
I
I
I
I
I
I
I
I
I
GAL22V10
GAL22V10
Specifications GAL22V10
Top View
Top View
SOIC
14
PLCC
2
High Performance E
28
16
26
18
25
23
21
19
I/O/Q
I/O/Q
I/O/Q
NC
I/O/Q
I/O/Q
I/O/Q
Generic Array Logic™
GAL22V10
PRESET
I/CLK
RESET
10
12
14
16
16
12
10
14
GND
8
8
I
I
I
I
I
I
I
I
I
I
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
OLMC
1
6
12
December 2006
22V10
2
DIP
GAL
CMOS PLD
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
24
13
18
Vcc
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I/O/Q
I
I/O/Q