CAT93C66SI Catalyst / ON Semiconductor, CAT93C66SI Datasheet - Page 7

• Manufacturer Part Number: CAT93C66SI
• Description: EEPROM (512x8) (256x16) 4K
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT93C66SI

• Memory Size: 4 Kbit
• Organization: 512 K x 8 or 256 K x 16
• Interface Type: Microwire
• Maximum Clock Frequency: 1 MHz
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 2.5 V, 6 V
• Operating Temperature: - 40 C to + 85 C
• Lead Free Status / Rohs Status: No RoHS Version Available

The format for all instructions sent to the device is a
logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46)/
/7-bit (93C57)/ 8-bit (93C56 or 93C66)/10-bit (93C86)
(an additional bit when organized X8) and for write
operations a 16-bit data field (8-bit for X8 organizations).
Note: This note is applicable only to 93C86. The Write,
Erase, Write all and Erase all instructions require PE=1.
If PE is left floating, 93C86 is in Program Enabled mode.
For Write Enable and Write Disable instruction PE=don’t
care.
Read
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C46/
56/57/66/86 will come out of the high impedance state
and, after sending an initial dummy zero bit, will begin
shifting out the data addressed (MSB first). The output
data bits will toggle on the rising edge of the SK clock and
are stable after the specified time delay (t
For the CAT93C56/57/66/86, after the initial data word
has been shifted out and CS remains asserted with the
SK clock continuing to toggle, the device will automatically
Figure 3. Write Instruction Timing
Figure 2b. Read Instruction Timing (93C56/57/66/86)
DO
CS
SK
DI
DO
CS
SK
DI
1
0
1
1
1
1
1
1
0
A N
HIGH-Z
A N
1
A N-1
A N–1
1
PD0
HIGH-Z
1
Dummy 0
or t
1
PD1
).
A 0
A 0
1
7
1
D 15 . . . D 0
or
D 7 . . . D 0
D N
increment to the next address and shift out the next data
word in a sequential READ mode. As long as CS is
continuously asserted and SK continues to toggle, the
device will keep incrementing to the next address
automatically until it reaches to the end of the address
space, then loops back to address 0. In the sequential
READ mode, only the initial data word is preceeded by
a dummy zero bit. All subsequent data words will follow
without a dummy zero bit.
Write
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of t
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93C46/56/57/66/86 can be determined by selecting
the device and polling the DO pin. Since this device
features Auto-Clear before write, it is NOT necessary to
erase a memory location before it is written into.
1
1
Address + 1
D 15 . . . D 0
or
D 7 . . . D 0
D 0
1
Don't Care
CSMIN
1
t SV
Address + 2
D 15 . . . D 0
or
D 7 . . . D 0
. The falling edge of CS will start the
1
t EW
t CSMIN
STATUS
VERIFY
1
BUSY
Address + n
D 15 . . .
or
D 7 . . .
READY
HIGH-Z
STANDBY
Doc. No. 1023, Rev. J
93C46/56/57/66/86 F05
t HZ