CAT24WC02J Catalyst / ON Semiconductor, CAT24WC02J Datasheet - Page 5

• Manufacturer Part Number: CAT24WC02J
• Description: EEPROM (256x8) 2k 2.5-6.0
• Manufacturer: Catalyst / ON Semiconductor

Specifications of CAT24WC02J

• Memory Size: 2 Kbit
• Organization: 256 K x 8
• Interface Type: I2C
• Maximum Clock Frequency: 0.1 MHz
• Access Time: 3500 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.5 V
• Maximum Operating Current: 3 mA
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8
• Minimum Operating Temperature: 0 C
• Operating Supply Voltage: 2.5 V, 6 V
• Operating Temperature: 0 C to + 70 C
• Lead Free Status / Rohs Status: No

Not Recommended for New Design,
Replace with CAT24C01
using either CAT24WC01 or CAT24WC02 device. All
three address pins are used for these densities. If only
one CAT24WC01 or CAT24WC02 is addressed on the
bus, all three address pins (A0, A1and A2) can be left
floating or connected to V
A total of four devices can be addressed on a single bus
when using CAT24WC04 device. Only A1 and A2
address pins are used with this device. The A0 address
pin is a no connect pin and can be tied to V
floating. If only one CAT24WC04 is being addressed on
the bus, the address pins (A1 and A2) can be left floating
or connected to V
Only two devices can be cascaded when using
CAT24WC08. The only address pin used with this
device is A2. The A0 and A1 address pins are no
connect pins and can be tied to V
one CAT24WC08 is being addressed on the bus, the
address pin (A2) can be left floating or connected to V
The CAT24WC16 is a stand alone device. In this case,
all address pins (A0, A1and A2) are no connect pins and
can be tied to V
WP: Write Protect
If the WP pin is tied to V
becomes Write Protected (READ only). When the WP
pin is tied to V
operations are allowed to the device.
I
The following defines the features of the I
(1) Data transfer may be initiated only when the bus is
(2) During a data transfer, the data line must remain
Figure 4. Acknowledge Timing
© Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
2
C Bus Protocol
not busy.
FROM TRANSMITTER
SS
SS
FROM RECEIVER
SS
or left floating.
DATA OUTPUT
DATA OUTPUT
.
or left floating normal read/write
SCL FROM
MASTER
SS
CC
.
the entire memory array
SS
START
or left floating. If only
2
C bus protocol:
SS
1
or left
SS
.
5
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC01/02/04/08/16
monitor the SDA and SCL lines and will not respond until
this condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master then sends the address
of the particular slave device it is requesting. The four
most significant bits of the 8-bit slave address are fixed
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).
The next three significant bits (A2, A1, A0) are the device
address bits and define which device or which part of the
device the Master is accessing. Up to eight CAT24WC01/
02, four CAT24WC04, two CAT24WC08, and one
CAT24WC16 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC01/02/04/08/16 monitors
the bus and responds with an acknowledge (on the SDA
line) when its address matches the transmitted slave
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
8
ACKNOWLEDGE
CAT24WC01/02/04/08/16
9
Doc. No. 1022, Rev. N
5020 FHD F06