A25L010-F AMIC, A25L010-F Datasheet
A25L010-F
Specifications of A25L010-F
Related parts for A25L010-F
A25L010-F Summary of contents
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... CE 1.4 Add packing description in Part Numbering Scheme 1.5 P30: Change Data Retention and Endurance value from Max. to Min. P37: Add A25L512V-UF, A25L010V-UF and A25L020V-UF in the ordering information 1.6 Add 8-pin USON (2*3mm) package type (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series 2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory ...
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... Clock Rate (maximum) Deep Power-down Mode 25µA (Max.) Stand-by current 25µA (Max.) GENERAL DESCRIPTION The A25L020/A25L010/A25L512 are 2M/1M/512K bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction ...
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... S C DIO DO Address register and Counter (December, 2010, Version 1. HOLD C DIO High Voltage Generator I/O Shift Register 256 Byte Data Buffer 3FFFFh (2M), 1FFFFh (1M) FFFFh (512K) 00000h 256 Byte (Page Size) X Decoder 2 A25L020/A25L010/A25L512 Series USON8 Connections A25L020/ A25L010/ A25L512 HOLD DIO SS Status ...
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... Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select ( Write Protect ( to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1, and BP0 bits of the Status Register). 3 A25L020/A25L010/A25L512 Series Logic Symbol V CC DIO C A25L020/ ...
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... C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= DIO SPI Memory Device S W HOLD HOLD ) signals should be driven, High or Low as appropriate MSB DO 4 A25L020/A25L010/A25L512 Series C DO DIO C DO SPI Memory SPI Memory Device S W HOLD S MSB AMIC Technology Corp. DIO Device W HOLD ...
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... Write, Program or Erase instructions. (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Status Register The Status Register contains a number of status and control bits that can be read or set (as appropriate) by specific instructions ...
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... Note: 1. The device is ready to accept a Chip Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0 (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Protected Area None Upper fourth (block: 3) Upper half (two blocks All blocks (four blocks Protected Area None Upper half (block: 1) ...
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... Figure 3. Hold Condition Activation C HOLD (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Serial Clock (C) next goes Low. This is shown in Figure 3. During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DIO) and Serial Clock (C) are Don’t Care. ...
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... Table 2. Memory Organization A25L020 Address Table Block Sector A25L010 MEMORY ORGANIZATION The memory is organized as: 131,072 bytes (8 bits each) 2 64-Kbytes blocks 32 4-Kbytes sectors 512 pages (256 bytes each). Table 3. Memory Organization A25L010 Address Table Block Sector (December, 2010, Version 1.6) ...
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... A25L512 Address Table Block Sector (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block, or Chip Erasable (bits are erased from but not Page Erasable. Address Range F000h 3000h 2000h 1000h 0000h AMIC Technology Corp ...
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... A25L020/A25L010/A25L512 Series One-byte Address Dummy Bytes 06h 0 04h 0 05h 0 01h 0 03h 3 0Bh 3 3Bh ...
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... Low, sending the instruction code, and then driving Chip The Write Enable Latch (WEL) bit is reset under the following conditions: Figure 5. Write Disable (WRDI) Instruction Sequence (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series The Write Enable (WREN) instruction is entered by driving Chip Select ( driving Chip Select ( S ...
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... Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution Status Register Out MSB 12 A25L020/A25L010/A25L512 Series W ) signal allow the device to be put in the Status Register Out MSB AMIC Technology Corp signal. ...
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... Register Write Disable (SRWD) bit and Write Protect ( signal allow the device to be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered initiated. While the Instruction 7 High Impedance MSB 13 A25L020/A25L010/A25L512 Series Status Register AMIC Technology Corp ...
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... Write Protect ( If Write Protect ( Protected Mode (HPM) can never be activated, and only the Software Protected Mode (SPM), using the Block Protect (BP2, BP1, BP0) bits of the Status Register, can be used. 14 A25L020/A25L010/A25L512 Series Memory Content 1 Protected Area Unprotected Area Protected against Page ...
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... DIO High Impedance DO Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series therefore, be read with a single Read Data Bytes (READ Low ...
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... DIO DO Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) Speed (FAST_READ) instruction. When the highest address S ) Low ...
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... DIO DO Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) accomplished by adding eight “dummy” clocks after the 24-bit address as shown in figure 10. The dummy clocks allow the device’ ...
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... DIO DO Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) frequency accomplished by adding four “dummy” clocks after the 24-bit address as shown in figure 11 ...
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... MSB Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) programmed correctly within the same page. If less than 256 ...
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... C DIO Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series instruction is not executed. As soon as Chip Select ( ...
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... C DIO Note: Address bits A23 to A18 are Don’t Care, for A25L020. Address bits A23 to A17 are Don’t Care, for A25L010. Address bits A23 to A16 are Don’t Care, for A25L512 (December, 2010, Version 1.6) instruction is not executed. As soon as Chip Select ( ...
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... Figure 15. Chip Erase (CE) Instruction Sequence S C DIO (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series is not executed. As soon as Chip Select ( the self-timed Chip Erase cycle (whose duration is t initiated. While the Chip Erase cycle is in progress, the Status Register may be read to check the value of the Write In Progress (WIP) bit ...
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... Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress. Instruction Stand-by Mode 23 A25L020/A25L010/A25L512 Series S ) Low, followed by the instruction code must be driven Low S ) must be driven High after the eighth bit of the ...
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... Low. and execute instructions. Device Identification Memory Type 30h Manufacture ID Memory Type High at any time during data output driven High, the device is put in the Memory Capacity 12h (A25L020) 11h (A25L010) 10h (A25L512 Memory Capacity AMIC Technology Corp. ...
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... Instruction 2 Dummy Bytes MSB (1) ADD Manufacturer MSB 25 A25L020/A25L010/A25L512 Series S ) High at any time during driven High, the device is put in the Device Identification 11h (A25L020) 10h (A25L010) 05h (A25L512 Device MSB AMIC Technology Corp. MSB ...
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... C Instruction DIO High Impedance DO Note: The value of the 8-bit Electronic Signature, for the A25L020 is 11h, A25L010 is 10h, A25L512 is 05h. (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series edge of Serial Clock (C). Then, the 8-bit Electronic Signature, and Read stored in the memory, is shifted out on Serial Data Output (DO), each bit being shifted out during the falling edge of Serial Clock (C) ...
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... Figure 20.), still insures that the device is put into Stand-by Power mode. If the device was not pre- viously in the Deep Power-down mode, the transition to the Stand-by Power mode is immediate. If the device was (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Instruction Deep Power-down Mode ...
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... Power-down occurs (min while a Write, Program or Erase cycle is in progress, some data corruption can result A25L020/A25L010/A25L512 Series t after V passed the VWI threshold PUW CC afterV passed the V (min) level VSL ...
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... Note: These parameters are characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Parameter 29 Min. Max. ...
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... Input Capacitance (other pins) IN Note: Sampled only, not 100% tested (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series *Comments Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of ...
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... Page Program Cycle Time PP t Sector Erase Cycle Time SE t Block Erase Cycle Time BE Chip Erase Cycle Time of A25L020 t Chip Erase Cycle Time of A25L010 CE Chip Erase Cycle Time of A25L512 Note: 1. Max is for 85 ° This is preliminary data Table 16. AC Measurement Conditions Symbol C Load Capacitance L ...
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... Figure 22. AC Measurement I/O Waveform 0.8V 0.2V (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Input Levels Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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... Page Program Cycle Time pp t Sector Erase Cycle Time SE t Block Erase Cycle Time BE Chip Erase Cycle Time of A25L020 t Chip Erase Cycle Time of A25L010 CE Chip Erase Cycle Time of A25L512 Note must be greater than or equal Value guaranteed by characterization, not 100% tested in production. 3. Expressed as a slew-rate. ...
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... Figure 23. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO (December, 2010, Version 1.6) tSLCH tCHDX MSB IN High Impedance High Impedance 34 A25L020/A25L010/A25L512 Series tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...
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... Figure 25. Hold Timing S C DIO DO HOLD Figure 26. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 35 tHHCH tHHQX tCL LSB OUT tQLQH tQHQL AMIC Technology Corp. tSHQZ ...
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... Part Numbering Scheme A25 X XXX * Optional (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series / Packing Blank: for DIP8 G: for SOP8 In Tube Q: for Tape & Reel Package Material Blank: normal F: PB free Temperature -40°C ~ +85°C Blank = 0°C ~ +70°C Package Type Blank = DIP 209 mil SOP 8 ...
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... A25L020O-UF A25L020M-F 100 A25L020M-UF A25L020V-F A25L020V-UF A25L020Q1 for industrial operating temperature range: -40 ° +85 ° C Blank is for commercial temperature range: 0 ° +70 ° C Part No. Speed (MHz) A25L010-F A25L010-UF A25L010O-F A25L010O-UF A25L010M-F 100 A25L010M-UF A25L010V-F A25L010V-UF A25L010Q1 for industrial operating temperature range: -40°C ~ +85°C Blank is for commercial temperature range: 0 ° ...
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... A25L512-UF A25L512O-F A25L512O-UF A25L512M-F 100 A25L512M-UF A25L512V-F A25L512V-UF A25L512Q1 for industrial operating temperature range: -40°C ~ +85°C Blank is for commercial temperature range: 0 ° +70 ° C (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Active Read Program/Erase Current Current Max. (mA) Max. (mA Standby Current Package Max. (μA) ...
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... L 0.125 - - E 0.345 - 0.385 A S 0.016 0.021 0.026 do not include mold flash or protrusions. 1 does not include dambar protrusion A25L020/A25L010/A25L512 Series Dimensions in mm Min Nom Max - - 4.57 0. 3.25 3.30 3.45 0.36 0.46 0.56 1.27 1.52 1.78 0.81 0.99 1.17 0.20 0.25 ...
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... Package Information SOP 8L (150mil) Outline Dimensions e D (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series b ° 8 ° Dimensions in mm Symbol A 1.35~1.75 A 0.10~0. 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC H 5.80~6. 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions are in millimeters (max/min). ...
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... Package Information SOP 8L (209mil) Outline Dimensions (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series GAGE PLANE SEATING PLANE b Dimensions in mm Symbol Min Nom A 1.75 1.95 A 0.05 0. 1.70 1. 0.35 0.42 C 0.19 0.20 D 5.23 5.13 E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0 ...
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... E 0.1693 0.1732 0.1772 0.0256 - D 0.1142 0.1181 0.1220 L 0.0177 0.0236 0.0295 L - 0.0394 - 0.0039 θ - 0° 8° 42 A25L020/A25L010/A25L512 Series θ Dimensions in mm Min Nom Max - - 1.200 0.050 - 0.150 0.800 1.000 1.050 0.190 - 0.300 0.090 - 0.200 6.200 6.400 6.600 4.300 4.400 4.500 - 0.650 - 2 ...
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... E 0.004 0.008 0.012 0. 0.020 - e L 0.016 0.018 0.020 0. 0.006 1 L 0.012 - - 0.30 3 trace or pad on board. terminals. 43 A25L020/A25L010/A25L512 Series unit: inches/ Bottom View Dimensions in mm Nom Max 0.55 0.60 0 0.035 0.05 - 0.40 0.425 - 0.152 - 0.25 0.30 2.00 2.10 1.60 1.70 3 ...