A29L040-70F AMIC, A29L040-70F Datasheet - Page 12

• Manufacturer Part Number: A29L040-70F
• Description: 58T1316
• Manufacturer: AMIC

Specifications of A29L040-70F

• Memory Type: Flash - NOR
• Memory Size: 4Mbit
• Memory Configuration: 512K X 8
• Interface Type: Parallel
• Supply Voltage Range: 2.7V To 3.6V
• Memory Case Style: DIP
• No. Of Pins: 32
• Rohs Compliant: Yes

Write Operation Status
Several bits, I/O
A29L040 to determine the status of a write operation. Table 5
and the following subsections describe the functions of these
status bits. I/O
determining whether a program or erase operation is complete or
in progress. These three bits are discussed first.
I/O
The
an Embedded Algorithm is in progress or completed, or whether
the device is in Erase Suspend.
rising edge of the final
command sequence.
During the Embedded Program algorithm, the device outputs on
I/O
status also applies to programming during Erase Suspend. When
the Embedded Program algorithm is complete, the device outputs
the datum programmed to I/O
program address to read valid status information on I/O
program address falls within a protected sector,
I/O
reading array data.
During the Embedded Erase algorithm,
"0" on I/O
if the device enters the Erase Suspend mode,
produces a "1" on I/O
datum output described for the Embedded Program algorithm:
the erase function changes all the bits in a sector to "1"; prior to
this, the device outputs the "complement," or "0." The system
must provide an address within any of the sectors selected for
erasure to read valid status information on I/O
After an erase command sequence is written, if all sectors
selected for erasing are protected,
for approximately 100μs, then the device returns to reading array
data. If not all selected sectors are protected, the Embedded
Erase algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
When the system detects I/O
to true data, it can read valid data at I/O
read cycles. This is because I/O
with I/O
the "AC Characteristics" section illustrates this. Table 5 shows
the outputs for
Polling algorithm.
(September, 2011, Version 1.6)
Data
7
7
7
: Data Polling
the complement of the datum programmed to I/O
Data
is active for approximately 2μs, then the device returns to
Polling Timings (During Embedded Algorithms) figure in
0
- I/O
7
. When the Embedded Erase algorithm is complete, or
Polling bit, I/O
6
while Output Enable (
Data
2
7
, I/O
, I/O
7
3
Polling on I/O
.This is analogous to the complement/true
, I/O
6
7
and I/O
, indicates to the host system whether
WE
5
, I/O
7
has changed from the complement
7
pulse in the program or erase
. The system must provide the
6
, and I/O
7
Data
2
Data
may change asynchronously
7
each offer a method for
. Figure 3 shows the
OE
Data
Polling is valid after the
7
Polling on I/O
) is asserted low. The
- I/O
7,
are provided in the
7
Polling produces a
.
0
Data
on the following
Data
7
. This I/O
Polling on
7
is active
Polling
7
Data
. If a
11
7
Note :
1. VA = Valid address for programming. During a sector
2. I/O
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
I/O
No
7
7
should be rechecked even if I/O
may change simultaneously with I/O
Figure 3. Data Polling Algorithm
Read I/O
Read I/O
Address = VA
Address = VA
I/O
I/O
I/O
START
7
7
AMIC Technology, Corp.
FAIL
= Data ?
= Data ?
5
= 1?
7
7
-I/O
- I/O
Yes
No
No
0
A29L040 Series
0
5
= "1" because
Yes
Yes
5
.
PASS