DSPD56367AG150 Freescale Semiconductor, DSPD56367AG150 Datasheet
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
DSPD56367AG150
Specifications of DSPD56367AG150
Available stocks
Related parts for DSPD56367AG150
DSPD56367AG150 Summary of contents
Page 1
... MHz clock at 1.5 V. This document contains information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2001, 2002, 2003, 2004, 2005, 2006, 2007. All rights reserved. Document Number: DSP56367 Rev ...
Page 2
... ROM 32K YAB EXTERNAL 18 XAB ADDRESS PAB BUS DAB ADDRESS SWITCH DRAM & SRAM BUS 10 INTERFACE & CONTROL I - CACHE EXTERNAL 24 DATA BUS SWITCH DATA POWER MNGMNT DATA ALU 24X24 + 56 -> 56-BIT MAC 4 JTAG BARREL SHIFTER OnCE™ 24 BITS BUS Freescale Semiconductor ...
Page 3
... Simultaneous glueless interface to SRAM and DRAM. 1.5 Peripheral modules • Serial Audio Interface (ESAI receivers and transmitters, master or slave. I AC97, network and other programmable protocols. Freescale Semiconductor i : i=0 to 7). Reduces clock noise. DSP56367 Technical Data, Rev. 2.1 Overview 2 S, Sony, ...
Page 4
... Brief description of the chip DSP56367 User’s Manual Electrical and timing specifications; pin and package descriptions Input Output Buffer Information Specification DSP56367 Technical Data, Rev. 2 Order Number DSP56300FM DSP56367P DSP56367UM DSP56367 For software or simulation models, contact sales www.freescale.com. Freescale Semiconductor ...
Page 5
... Port C signals are the GPIO port signals which are multiplexed with the ESAI signals. 4 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals. 5 Port D signals are the GPIO port signals which are multiplexed with the DAX signals. Freescale Semiconductor 2-1. 1 Port A 2 ...
Page 6
... HACK/HRRQ [PB15] VCCH GNDH SCKT[PC3] FST [PC4] HCKT [PC5] SCKR [PC0] FSR [PC1] HCKR [PC2] SDO0[PC11] / SDO0_1[PE11] SDO1[PC10] / SDO1_1[PE10] SDO2/SDI3[PC9] / SDO2_1/SDI3_1[PE9] SDO3/SDI2[PC8] / SDO3_1/SDI2_1[PE8] SDO4/SDI1 [PC7] SDO5/SDI0 [PC6] SCKT_1[PE3] FS T_1[PE4] SCKR_1[PE0] FSR_1[PE1] SDO4_1/SDI1_1[PE7] SDO5_1/SDI0_1[PE6] VCCS (2) GNDS (2) MOSI/HA0 SS/HA2 MISO/SDA SCK/SCL HREQ Freescale Semiconductor ...
Page 7
... Data Bus Ground—GND D must be tied externally to all other chip ground connections. The user must provide adequate external decoupling capacitors. There are four GND Freescale Semiconductor Table 2-2 Power Inputs Description is V dedicated for PLL use. The voltage should be well-regulated and the input should isolated power for the internal processing logic ...
Page 8
... Otherwise, the signals are tri-stated. To minimize power dissipation, A0–A17 do not change state when external memory spaces are not being accessed. DSP56367 Technical Data, Rev. 2.1 connections CCP , GND, or left floating. CC Freescale Semiconductor ...
Page 9
... Tri-Stated TA Input Ignored Input Transfer Acknowledge—If the DSP is the bus master and there is no external bus Freescale Semiconductor Table 2-6 External Data Bus Signals Reset Data Bus—When the DSP is the bus master, D0–D23 are active-high, bidirectional input/outputs that provide the bidirectional data bus for external program and data memory accesses. Otherwise, D0– ...
Page 10
... The deassertion done by an “active pull-up” method (i.e driven high and then released and held high by an external pull-up resistor). For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the OMR register must be set. BB requires an external pull-up resistor. DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 11
... Input Input RESET Input Input Freescale Semiconductor Table 2-8 Interrupt and Mode Control Signal Description Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA selects the initial chip operating mode during hardware reset and becomes a level-sensitive or negative-edge-triggered, maskable interrupt request input during normal instruction processing ...
Page 12
... Port B 9—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Signal Description Freescale Semiconductor ...
Page 13
... HWR/ Input HWR PB12 Input, Output, or Disconnected Freescale Semiconductor Table 2-9 Host Interface (continued) Reset GPIO Host Address Input 2—When the HDI08 is programmed to interface a non-multiplexed host bus and the HI function is selected, this signal is line 2 of the host address (HA2) input bus. ...
Page 14
... Port B 15—When the HDI08 is configured as GPIO, this signal is individually programmed as input, output, or internally disconnected. The default state after reset for this signal is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Signal Description Freescale Semiconductor ...
Page 15
... Output SDA Input or Open-Drain Output Freescale Semiconductor Table 2-10 Serial Host Interface Signals Signal Description SPI Serial Clock—The SCK signal is an output when the SPI is configured as a master and a Schmitt-trigger input when the SPI is configured as a slave. When the SPI is configured as a master, the SCK signal is derived from the internal SHI clock generator ...
Page 16
... This signal is tri-stated during hardware, software, personal reset, or when the HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for external pull-up in this state. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2 master mode Slave mode, the HA2 signal is used master mode. Freescale Semiconductor ...
Page 17
... Disconnected PC1 Input, Output, or Disconnected Freescale Semiconductor Signal Description High Frequency Clock for Receiver—When programmed as an input, this signal provides a high frequency clock source for the ESAI receiver as an alternate to the DSP core clock. When programmed as an output, this signal can serve as a high-frequency sample clock (e ...
Page 18
... RX0 serial receive shift register. Port C 6—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input is 3.3V tolerant. DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 19
... Disconnected PC10/ Input, Output, or PE10 disconnected Freescale Semiconductor Signal Description Serial Data Output 4—When programmed as a transmitter, SDO4 is used to transmit data from the TX4 serial transmit shift register. Serial Data Input 1—When programmed as a receiver, SDI1 is used to receive serial data into the RX1 serial receive shift register. ...
Page 20
... ESAI transmit clock control register (TCCR). Port E 4—When the ESAI is configured as GPIO, this signal is individually programmable as input, output, or internally disconnected. The default state after reset is GPIO disconnected. This input cannot tolerate 3.3V. DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 21
... Input PE7 Input, Output, or Disconnected Freescale Semiconductor Signal Description Receiver Serial Clock_1—SCKR provides the receiver serial bit clock for the ESAI. The SCKR operates as a clock input or output used by all the enabled receivers in the asynchronous mode (SYN=0 serial flag 0 pin in the synchronous mode (SYN=1) ...
Page 22
... If TIO0 is not being used recommended to either define it as GPIO output immediately at the beginning of operation or leave it defined as GPIO input but connected to Vcc through a pull-up resistor in order to ensure a stable logic level at this input. This input is 3.3 V tolerant. DSP56367 Technical Data, Rev. 2.1 Signal Description Signal Description Freescale Semiconductor ...
Page 23
... TDO Output Tri-Stated TMS Input Input Freescale Semiconductor Table 2-15 JTAG/OnCE Interface Signal Description Test Clock—TCK is a test clock input signal used to synchronize the JTAG test logic. It has an internal pull-up resistor. This input is 3.3V tolerant. Test Data Input—TDI is a test data serial input signal used for test instructions and data ...
Page 24
... JTAG/OnCE Interface 2-20 NOTES DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 25
... Therefore, a “maximum” value for a specification will never occur in the same device that has a “minimum” value for another specification; adding a maximum to a minimum represents a condition that can never exist. Freescale Semiconductor NOTE CAUTION ). The suggested value for a pull-up or ...
Page 26
... Table 3-2 Thermal Characteristics Symbol 1,2 R θ θJC 4 DSP56367 Technical Data, Rev. 2 Value − 0 2.0 − 0 4.0 − GND 0 0 − − +125 TQFP Value Unit or θ ° 45.0 C θ ° 10.0 C/W JC Ψ ° 3.0 C/W JT Freescale Semiconductor Unit ° C ° C ...
Page 27
... PLL supply current 6 Input capacitance 1.8 V ± 5 –40°C to +95°C, C CCQL J J All other V = 3.3 V ± 5 –40°C to +95° Refers to MODA/IRQA, MODB/IRQB, MODC/IRQC, and MODD/IRQD pins. Freescale Semiconductor Table 3-3 DC Electrical Characteristics Symbol IHP /SHI (SPI mode) V IHP 0.8 × V ...
Page 28
... MF)/(PDF × DF) — Ef/2 — ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — C DF/MF ET — C 0.51 × ET × PDF × — C DF/MF 0.53 × ET × PDF × — C DF/MF × PDF × DF/MF ET — C Freescale Semiconductor ...
Page 29
... With PLL disabled (46.7%–53.3% duty cycle • With PLL enabled (42.5%–57.5% duty cycle EXTAL input low • With PLL disabled (46.7%–53.3% duty cycle • With PLL enabled (42.5%–57.5% duty cycle Freescale Semiconductor Table 3-4 Internal Clocks (continued) Symbol Min T — — ...
Page 30
... MF × 830 DSP56367 Technical Data, Rev. 2.1 Symbol Min Max ET C ∞ 6.7 ns 273.1 µs 6 CYC ∞ 13.33 ns 8.53 µs 6.67 ns Max Unit 300 MHz pF (MF × 780) − 140 MF × 1470 ). The recommended value in pF for CCP Freescale Semiconductor ...
Page 31
... Delay from address output valid caused by first interrupt instruction execute to interrupt request deassertion for level sensitive fast interrupts 20 Delay from RD assertion to interrupt request deassertion for level sensitive fast interrupts Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Expression 2 50 × ET 1000 × ET 75000 × ET 75000 × ET 2.5 × ...
Page 32
... C + 1.0 62.7 — 5.0 — 170.0 C − 0.1 3.9 — C × PDF + (128 K — — C × PDF + (23.75 — — C 51.7 58.3 C — — C × PDF + (20.5 — — C 36.7 — C — 80 — 53 — 53.0 C — 80.0 C Freescale Semiconductor ...
Page 33
... The maximum value for ET is 4096 (maximum MF) divided by the desired internal frequency (i.e., for 150 MHz 4096/150 MHz = 27.3 µs). During the stabilization period, T timing may vary as well. Freescale Semiconductor Reset, Stop, Mode Select, and Interrupt Timing Expression 4.25 × –40° 95°C, C ...
Page 34
... Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI 3-10 9 Reset Value Figure 3-2 Reset Timing First Interrupt Instruction Execution/Fetch First Interrupt Instruction Execution 18 b) General Purpose I/O Figure 3-3 External Fast Interrupt Timing DSP56367 Technical Data, Rev. 2 First Fetch AA0460 Freescale Semiconductor ...
Page 35
... IRQA, IRQB, IRQC, IRQD, NMI Figure 3-4 External Interrupt Timing (Negative Edge-Triggered) RESET MODA, MODB, MODC, MODD, PINIT IRQA A0–A17 Figure 3-6 Recovery from Stop State Using IRQA Interrupt Service Freescale Semiconductor Figure 3-5 Operating Mode Select Timing 24 25 DSP56367 Technical Data, Rev. 2.1 ...
Page 36
... C − 2.0[2 ≤ WS ≤ 3] 3.0 — C − 2.0[WS ≥ 4] 6.3 — C − 4.0 [2 ≤ WS ≤ 3] 9.3 — C − 4.0[WS ≥ 4] 19.3 — C − 4.0[2 ≤ WS ≤ 7] 4.3 — C − 4.0[WS ≥ 8] 11.0 — C Freescale Semiconductor Unit ...
Page 37
... WS ≤ 7] timing is specified for 2 wait states.) Two wait states is the minimum otherwise. 2 Timings 100, 107 are guaranteed by design, not tested the case of TA negation: timing 118 is relative to the deassertion edge were TA to remain active. Freescale Semiconductor Symbol (WS + 0.75) × ...
Page 38
... Figure 3-9 SRAM Read Access 100 107 101 102 114 108 Figure 3-10 SRAM Write Access DSP56367 Technical Data, Rev. 2.1 117 106 118 Data In AA0468 103 118 119 109 Data Out Freescale Semiconductor ...
Page 39
... Wait States 2 Wait States Figure 3-11 DRAM Page Mode Wait States Selection Guide Freescale Semiconductor Figure 3-11 and Figure 3-14 should be used for primary selection only. Note: This figure should be use for primary selection. For exact and detailed timings see the following tables. ...
Page 40
... C 3.75 × T − 4.3 33.2 — 3.25 × T − 4.3 28.2 — 0.5 × T − 4.0 1.0 — 2.5 × T − 4.0 21.0 — 1.25 × T − 4.3 8.2 — 3.5 × T − 4.0 31.0 — Freescale Semiconductor ...
Page 41
... Previous CAS deassertion to RAS deassertion 137 CAS assertion pulse width 138 Last CAS deassertion to RAS assertion • BRW[1–0] = 00, 01—Not applicable • BRW[1– • BRW[1– 139 CAS deassertion pulse width 140 Column address valid to CAS assertion Freescale Semiconductor Symbol 6 Symbol CAC OFF ...
Page 42
... C 3.5 × T − 4.0 31.0 — 1.25 × T − 4.3 8.2 — 4.5 × T − 4.0 41.0 — 3.25 × T − 5.7 — 26 0.0 — ns 0.75 × T – 1.5 6.0 — 0.25 × T — 2 equals PC and not t . OFF GZ Freescale Semiconductor ...
Page 43
... RAS CAS Row A0–A17 Add WR RD D0–D23 Figure 3-12 DRAM Page Mode Write Accesses Freescale Semiconductor 131 137 139 140 141 Column Column Address Address 151 144 145 146 155 150 149 Data Out Data Out DSP56367 Technical Data, Rev. 2.1 ...
Page 44
... Figure 3-13 DRAM Page Mode Read Accesses 3-20 131 137 139 140 141 Column Column Address Address 143 133 153 Data In Data In DSP56367 Technical Data, Rev. 2.1 136 135 138 142 Last Column Address 132 152 134 154 Data In AA0474 Freescale Semiconductor ...
Page 45
... CAS deassertion to data not valid (read hold time) 162 RAS deassertion to RAS assertion 163 RAS assertion pulse width 164 CAS assertion to RAS deassertion Freescale Semiconductor and detailed timings see the following tables. 120 66 80 100 11 Wait States 15 Wait States Symbol Expression 5 × ...
Page 46
... Freescale Semiconductor ...
Page 47
... RAS assertion to column address valid 169 CAS deassertion to RAS assertion 170 CAS deassertion pulse width 171 Row address valid to RAS assertion 172 RAS assertion to row address not valid Freescale Semiconductor Symbol Expression 4.5 × T − 4.0 t ROH C 4 × T − 7.5 ...
Page 48
... T − 4.0 11.0 — C 2.75 × T − 4.0 23.5 — C 11.5 × T − 4.0 111.0 — × T − 7.0 — 93.0 C 0.0 — 0.75 × T − 0.3 7.2 — C 0.25 × T — 2.5 C and not t . OFF GZ Freescale Semiconductor Unit ...
Page 49
... WR deassertion to CAS assertion 4 178 CAS deassertion to WR assertion 4 179 RAS deassertion to WR assertion 180 CAS assertion to WR deassertion 181 RAS assertion to WR deassertion 182 WR assertion pulse width Freescale Semiconductor Symbol Expression 16 × 8.25 × RAC 4.75 × CAC 5.5 × OFF 6.25 × ...
Page 50
... T − 4.0 11.0 — C 4.75 × T − 4.0 43.5 — C 15.5 × T − 4.0 151.0 — × T − 5.7 — 134.3 C 0.0 — 0.75 × T – 1.5 6.0 — C 0.25 × T — 2.5 C and not t . OFF GZ Freescale Semiconductor Unit ...
Page 51
... RAS 169 CAS A0–A17 WR RD D0–D23 Figure 3-15 DRAM Out-of-Page Read Access Freescale Semiconductor 157 163 165 167 164 168 170 166 171 173 175 Row Address Column Address 172 176 177 191 160 159 158 192 DSP56367 Technical Data, Rev. 2.1 ...
Page 52
... Row Address Column Address 181 175 188 180 182 184 183 187 186 185 194 Data Out DSP56367 Technical Data, Rev. 2.1 162 174 195 AA0477 Freescale Semiconductor ...
Page 53
... Bit 13 in the OMR register must be set to enter Asynchronous Arbitration mode Asynchronous Arbitration mode is active, none of the timings order to guarantee timings 250, and 251 recommended to assert BG inputs to different 56300 devices (on the same bus non overlap manner as shown in Freescale Semiconductor 157 163 162 165 189 ...
Page 54
... BG asserted, and BB negated, may cause another 56300 component to assume mastership at the same time. Therefore some non-overlap period between one BG input active to another BG input active is required. Timing 251 ensures that such a situation is avoided. 3-30 250 250+251 DSP56367 Technical Data, Rev. 2.1 251 Freescale Semiconductor ...
Page 55
... HACK read deassertion to output data high impedance 329 Output data hold time after read data strobe deassertion Output data hold time after HACK read deassertion 330 HCS assertion to read data strobe deassertion 331 HCS assertion to write data strobe deassertion Freescale Semiconductor after “Last Data Register” reads ...
Page 56
... T 6.7 — × T 13.4 — C — — 19.1 — — 300.0 2 × 19.1 32.5 — C 1.5 × 19.1 29.2 — C 0.0 — — — 20.2 — — 300.0 Freescale Semiconductor Unit ...
Page 57
... HD7–HD0 HOREQ Figure 3-20 Host Interrupt Vector Register (IVR) Read Timing Diagram HA0–HA2 HCS HRD, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-21 Read Timing Diagram, Non-Multiplexed Bus Freescale Semiconductor 317 327 329 326 336 337 330 317 318 328 ...
Page 58
... Parallel Host Interface (HDI08) Timing HA0–HA2 HCS HWR, HDS HD0–HD7 HOREQ, HRRQ, HTRQ Figure 3-22 Write Timing Diagram, Non-Multiplexed Bus 3-34 336 331 320 321 324 340 341 DSP56367 Technical Data, Rev. 2.1 337 333 325 339 AA0485 Freescale Semiconductor ...
Page 59
... HA8–HA10 322 HAS HRD, HDS HAD0–HAD7 HOREQ, HRRQ, HTRQ Figure 3-23 Read Timing Diagram, Multiplexed Bus Freescale Semiconductor 336 337 323 317 334 335 327 328 329 Address Data 326 340 341 DSP56367 Technical Data, Rev. 2.1 Parallel Host Interface (HDI08) Timing ...
Page 60
... Figure 3-25 Host DMA Write Timing Diagram 3-36 336 323 320 334 324 335 Data Address 340 341 342 343 344 320 321 TXH/M/L Write 324 325 Data Valid DSP56367 Technical Data, Rev. 2.1 321 325 339 AA0487 Freescale Semiconductor ...
Page 61
... Table 3-16 Serial Host Interface SPI Protocol Timing 1 No. Characteristics 140 Tolerable spike width on clock or data in 141 Minimum serial clock cycle = t 142 Serial clock high period 143 Serial clock low period Freescale Semiconductor HOREQ (Output) 343 342 317 HACK RXH (Input) Read 327 326 ...
Page 62
... C 2 × 210 — 223 11.7 — 61.7 — 106 112.7 — — 39.7 C 2.5 × — 46 120 — 136 217 — 233.8 C 2.5 × 46.8 — C 2.5 × 96.8 — 136 152.8 — C 2.5 × 46.8 — C Freescale Semiconductor Unit ...
Page 63
... The timing values calculated are based on simulation data at 150MHz. Tester restrictions limit SHI testing to lower clock frequencies. 3 Periodically sampled, not 100% tested SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 148 MISO (Input) MOSI (Output) 161 HREQ (Input) Freescale Semiconductor Filter 1 Mode Mode Slave — Master Bypassed Narrow Wide Master — Master — 143 ...
Page 64
... HREQ (Input) 3-40 143 142 144 142 144 143 148 149 MSB Valid 152 MSB 162 163 Figure 3-28 SPI Master Timing (CPHA = 1) DSP56367 Technical Data, Rev. 2.1 141 144 141 144 148 149 LSB Valid 153 LSB AA0272 Freescale Semiconductor ...
Page 65
... SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) 150 MISO (Output) 148 MOSI (Input) HREQ (Output) Freescale Semiconductor 143 142 144 146 142 144 143 154 152 153 153 MSB 149 MSB Valid 157 Figure 3-29 SPI Slave Timing (CPHA = 0) DSP56367 Technical Data, Rev. 2.1 ...
Page 66
... Standard Fast-Mode Min Max Min Max — 0 — 0 — 50 — 50 — 100 — 100 — 100 — 400 10 — 2.5 — 4.7 — 1.3 — 4.7 — 0.6 — 4.0 — 0.6 — Freescale Semiconductor Unit ns kHz µs µs µs µs ...
Page 67
... It is recommended to enable the wide filters when operating in the I 5 The timing values are derived from frequencies not exceeding 100 MHz recommended to enable the narrow filters when operating in the I Freescale Semiconductor 2 C Protocol Timing (continued) 2 Standard I C Symbol Expression ...
Page 68
... CCP DSP56367 Technical Data, Rev. 2 × HRS ) – and the filters selected should be chosen Table 3-18. × 45ns + R C × 135ns + R C × 223ns + environment = 8752ns × – = 53.7 × ( × – × – 8640ns Freescale Semiconductor ...
Page 69
... For internal clock • For external clock 433 RXC rising edge to FSR out (bl) high 434 RXC rising edge to FSR out (bl) low 435 RXC rising edge to FSR out (wr) high 436 RXC rising edge to FSR out (wr) low Freescale Semiconductor 171 176 175 180 178 ...
Page 70
... Freescale Semiconductor 6 Unit ...
Page 71
... FST(FST pin) = transmit frame sync FSR(FSR pin) = receive frame sync HCKT(HCKT pin) = transmit high frequency clock HCKR(HCKR pin) = receive high frequency clock 7 For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register. Freescale Semiconductor Symbol Expression 23 + 0.5 × — ...
Page 72
... In normal mode, the output flag state is asserted for the entire frame period. 3-48 430 432 446 447 450 454 454 452 First Bit 459 453 461 458 461 460 462 Figure 3-32 ESAI Transmitter Timing DSP56367 Technical Data, Rev. 2.1 451 455 Last Bit 456 See Note AA0490 Freescale Semiconductor ...
Page 73
... RXC (Input/Output) FSR (Bit) Out FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In HCKT SCKT (output) Freescale Semiconductor 430 431 432 433 434 437 439 First Bit 441 443 442 444 Figure 3-33 ESAI Receiver Timing 463 464 Figure 3-34 ESAI HCKT Timing DSP56367 Technical Data, Rev ...
Page 74
... Figure 3-35 ESAI HCKR Timing Expression × 0.5 × 0.5 × 1.5 × 220 221 DSP56367 Technical Data, Rev. 2.1 150 MHz Unit Min Max — 75 MHz 13.4 — ns 3.4 — ns 3.4 — ns — 10.0 ns 222 AA1280 Freescale Semiconductor ...
Page 75
... Fetch to EXTAL edge before GPIO change 495 GPIO out rise time 496 GPIO out fall time 1.8 V ± 0. -40°C to +95° Valid only when PLL enabled with multiplication factor equal to one. Freescale Semiconductor 1 Table 3-21 Timer Timing Expression 2 × 2 × 2 480 ...
Page 76
... Table 3-23 JTAG Timing Characteristics × 3); maximum 22 MHz) C DSP56367 Technical Data, Rev. 2.1 490 491 All frequencies Unit Min Max 0.0 22.0 MHz 45.0 — ns 20.0 — ns 0.0 3.0 ns 5.0 — ns 24.0 — ns 0.0 40.0 ns 0.0 40.0 ns 5.0 — ns Freescale Semiconductor ...
Page 77
... Figure 3-39 Test Clock Input Timing Diagram TCK V (Input) IL Data Inputs Data Outputs Data Outputs Data Outputs Figure 3-40 Boundary Scan (JTAG) Timing Diagram Freescale Semiconductor 1, 2 Table 3-23 JTAG Timing (continued) Characteristics = 501 502 504 Input Data Valid ...
Page 78
... JTAG Timing TCK V (Input) IL TDI TMS (Input) TDO (Output) TDO (Output) TDO (Output) Figure 3-41 Test Access Port Timing Diagram 3-54 508 Input Data Valid 510 Output Data Valid 511 510 Output Data Valid DSP56367 Technical Data, Rev. 2 509 AA0498 Freescale Semiconductor ...
Page 79
... The DSP56367 is available in a 144-pin LQFP package. assignments for the packages. 4.1.1 LQFP Package Description Top view of the 144-pin LQFP package is shown in shown in Figure 4-2. Freescale Semiconductor Table 4-1and Figure 4-1 with its pin-outs. The package drawing is DSP56367 Technical Data, Rev. 2.1 Table 4-2 show the pin/name ...
Page 80
... Figure 4-1 144-pin package DSP56367 Technical Data, Rev. 2.1 108 D6 107 D5 106 D4 105 D3 104 GNDD 103 VCCD 102 D2 101 D1 100 D0 99 A17 98 A16 97 A15 96 GNDA 95 VCCQH 94 A14 93 A13 92 A12 91 VCCQL 90 GNDQ 89 A11 88 A10 87 GNDA 86 VCCA GNDA 80 VCCA GNDA 74 VCCA 73 A1 Freescale Semiconductor ...
Page 81
... D2 102 GNDD D3 105 GNDH D4 106 GNDP D5 107 GNDQ D6 108 GNDQ D7 109 GNDQ D8 110 GNDQ Freescale Semiconductor Table 4-1 Signal Identification by Name Pin Signal Name No. 113 GNDS 114 GNDS 115 HA8/HA1 116 HA9/HA2 117 HACK/HRRQ 118 HAD0 121 HAD1 122 HAD2 123 ...
Page 82
... D19 126 VCCQL 127 GNDQ 128 D20 129 VCCD 130 GNDD 131 D21 132 D22 133 D23 134 MODD/IRQD# 135 MODC/IRQC# 136 MODB/IRQB# 137 MODA/IRQA# 138 SDO4_1/SDI1_1 139 TDO 140 TDI 141 TCK 142 TMS 143 MOSI/HA0 144 MISO/SDA Freescale Semiconductor ...
Page 83
... LQFP Package Mechanical Drawing Figure 4-2 DSP56367 144-pin LQFP Package ( Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information 4-5 ...
Page 84
... Pin-out and Package Information Figure 4-3 DSP56367 144-pin LQFP Package ( 4-6 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 85
... Figure 4-4 DSP56367 144-pin LQFP Package ( Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 Pin-out and Package Information 4-7 ...
Page 86
... Pin-out and Package Information 4-8 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 87
... Again, if the estimations obtained from R the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages. Freescale Semiconductor , in °C can be obtained from the following equation × ...
Page 88
... IRQB, IRQD, and TA pins. Maximum PCB trace lengths on the order inches) are recommended. 5 determined by a thermocouple, the thermal resistance T CAUTION ). The suggested value for a pull-up or pull-down resistor CC power source to GND. CC DSP56367 Technical Data, Rev. 2.1 – has been defined JT pin on the DSP and from CC and GND. CC Freescale Semiconductor and CC ...
Page 89
... Minimize external memory accesses and use internal memory accesses. • Minimize the number of pins that are switching. • Minimize the capacitive load on the pins. • Connect the unused inputs to pull-up or pull-down resistors. • Disable unused peripherals. Freescale Semiconductor and GND circuits. CC CCP × × Example 1 ...
Page 90
... The phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed values. 5-4 Appendix A, "Power Consumption ⁄ MHz = I – I typF2 typF1 NOTE DSP56367 Technical Data, Rev. 2.1 ⁄ – Freescale Semiconductor ...
Page 91
... Default: 1 w.s (SRAM) ; movep #$0d0000,x:M_PCTL ; ; Load the program ; move #INT_PROG,r0 move #PROG_START,r1 do #(PROG_END-PROG_START),PLOAD_LOOP move p:(r1)+,x0 move x0,p:(r0)+ nop PLOAD_LOOP ; ; Load the X-data ; move #INT_XDAT,r0 move #XDAT_START,r1 Freescale Semiconductor ; XTAL disable ; PLL enable ; CLKOUT disable DSP56367 Technical Data, Rev. 2.1 A-1 ...
Page 92
... PROG_END nop nop XDAT_START ; org x:0 dc $262EB9 dc $86F2FE dc $E56A5F dc $616CAC A-2 ; ebd x:(r0)+,x1 y:(r4)+,y1 x:(r0)+,x0 y:(r4)+,y0 x:(r0)+,x1 y:(r4)+,y0 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 93
... Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 A-3 ...
Page 94
... A-4 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 95
... YDAT_END Freescale Semiconductor DSP56367 Technical Data, Rev. 2.1 A-5 ...
Page 96
... A-6 NOTES DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 97
... PLL 4 power consumption 3 thermal 1 Digital Audio Transmitter 18 DRAM out of page Freescale Semiconductor wait states selection guide 21 write access 28 out of page and refresh timings 11 wait states 23 15 wait states 25 4 wait states 21 Page mode read accesses 20 wait states selection guide 15 ...
Page 98
... P package TQFP description 1, 4 Phase Lock Loop 6 PLL 4, 6 Characteristics 6 performance issues 4 PLL design considerations 4 PLL performance issues 4 Port A 4 Port Port C 13, 16 Port D 18 Power 2 power consumption design considerations 3 DSP56367 Technical Data, Rev. 2.1 Freescale Semiconductor ...
Page 99
... Enhanced Serial Audio Interface (ESAI) 48 General Purpose I/O (GPIO) Timing 45 OnCE™ (On Chip Emulator) Timing 45 Serial Host Interface (SHI) SPI Protocol Tim- ing 37 Serial Host Interface (SHI) Timing 37 timing Freescale Semiconductor interrupt 7 mode select 7 Reset 7 Stop 7 TQFP pin list by number 4 pin-out drawing (top) 1 DSP56367 Technical Data, Rev ...
Page 100
... Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use ...