LE9502BTC Zarlink, LE9502BTC Datasheet - Page 6

• Manufacturer Part Number: LE9502BTC
• Description: SLIC 2-CH 63dB 3.3V 44-Pin TQFP Tray
• Manufacturer: Zarlink

Specifications of LE9502BTC

• Package: 44TQFP
• Number Of Channels Per Chip: 2
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Minimum Operating Supply Voltage: 3.13 V
• Typical Operating Supply Voltage: 3.3 V
• Typical Supply Current: 7.5 mA

For the reference schematic, Zetex part FZT955 in a SOT-223 package is used. Its V
and overhead voltage of the regulator allows a robust 70 Vpk ringing signal into a 5 REN load with V
Switcher Controller
The switcher controller’s main function is to provide a negative power supply (V
wire interface. As the Tip and Ring voltage decreases, the switcher will likewise lower V
because the device is not forced to maintain static supply voltage in all states.
The switching power supply controller uses a discontinuous mode, buck-boost voltage converter topology. The frequency of
operation is set by the ISET resistor and the VRAMP capacitor values. An external clock with approximately a 10% duty cycle
drives the gate (base) of a small-signal FET which is used to reset the VRAMP capacitor voltage, creating the ramp voltage used
internally by the switching power supply control circuitry. This clock signal controls the switching supply's operating frequency.
The switcher circuit is nominally designed for 85 kHz operation based on the
The duty cycle of the switching transistors is continuously variable up to 90% depending on the magnitude of the error voltage
on the compensation (CHS) pin. The error signal on CHS is compared to the ramp signal. The ramp rate of the VRAMP signal is
set by the ISET resistor (R
Conditioning
where I
provided in the specification section, f
calculated value for C
recommended for C
When the external clock signal goes from a logic Low to a logic High, it will pull VRAMP voltage low which causes internal clock
(from the square wave converter) to go Low, turning on the external power switch. When the external clock signal goes from High
to Low, C
from the square wave converter will reset the current limit latch getting it ready for the next cycle and turn off the external power
switch. Also on a cycle-by-cycle basis, one of the following three events will shut off the power switch, depending on which event
occurs first:
Cycle-by-cycle current limiting is provided by the current sense ILS
the resistor R
latch and shut off the external switch drive until the next time the VRAMP pin is pulled Low to reset the latch. Thus the peak
inductor current, and also peak switching converter power output can be controlled on a cycle-by-cycle basis and set by the
equation I
This sensing configuration has the added benefit that if the clock signal is removed for some reason, the power switch cannot be
left on indefinitely. Leaving the ILS
recommended.
A leading edge blanking filter is added at the output of the latch to ignore the first 150 ns of a current limit event. This feature is
used to ignore a false current trip that may be caused by the power switch driving the reverse recovery charge (Q
external power rectifier.
The on chip driver is designed to drive either an external PNP or a PMOS power device. Its output drive is clamped between
7-9 V below V
additional resistance should be added from the SD
drive for optimal efficiency.
When using a PMOS power switch, the SD
PMOS device, and an internal clamp will limit the drive between 7-9 V. To keep system losses to a minimum, it is recommended
that low gate charge be given higher consideration over low r
a) The VRAMP voltage exceeds the error voltage that is integrated on the CHS node (normal voltage feedback operation.)
b) The VRAMP voltage exceeds the internal voltage threshold.
c) The power switch current limit threshold is reached (set by R
RAMP_min
RAMP
LIM
LIM
= (VT
SW
on page
will charge up. When the VRAMP voltage exceeds internal voltage threshold, the rising edge of the internal clock
. If this pin exceeds VT
, and can source or sink approximately 100 mA. The driver has approximately 50 Ω of source resistance. The
is the current going through C
ILS
RAMP
RAMP
)/R
9) before using the following equation to calculate C
.
LIM
SET
.
is the maximum value that can guarantee the switcher to operate. A NPO dielectric capacitor is
C
) and the VRAMP capacitor (C
RAMP_max
i
pin unconnected or shorting this pin to VSW will disable current limiting, but is not
CHCLK
ILS
=
, nominally −0.28 V with respect to V
i
I
RAMP_min
pin will be able to drive approximately 100 mA of drive current to the gate of the
is the frequency of the chopper clock, and R
RAMP
i
Zarlink Semiconductor Inc.
pin to the base of the external power device if a PNP is used to limit base
•
, t
[
(
CHCLK_max
100% t
DS(on)
–
6
RAMP
CHCLK_max
i
when selecting a power PMOS device for your application.
pin which senses the external power switch current through
). A 1% R
is maximum duration of Chopper Clock High Duty Cycle
LIM
).
)
RAMP
⁄
(
Application Circuit
f
CHCLK
SET
SW
REG
, the switching supply will set the current limit
resistor should be chosen first (see
CEO
) that tracks Tip and Ring voltage for the 2-
•
REG
R
SET_max
rating is 140 V. The switching efficiency
. In doing so, the switcher saves power
SET_max
)
]
on page
SW
is R
= 12 V.
SET_nom
20.
* 1.01. The
RR
) of the
Signal