LE77D112BTC Zarlink, LE77D112BTC Datasheet - Page 7

• Manufacturer Part Number: LE77D112BTC
• Description: SLIC 1-CH 63dB 3.3V 44-Pin eTQFP Tray
• Manufacturer: Zarlink

Specifications of LE77D112BTC

• Package: 44eTQFP
• Number Of Channels Per Chip: 1
• Polarity Reversal: Yes
• Longitudinal Balanced: 63 dB
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

For this application, R
power available during the Ringing state when the converter operates at the highest currents. The capacitors C
very low ESR film capacitors to minimize ripple and noise on V
capacitors, and hence a faster slew rate. Reduction of switcher noise is accomplished by using lower ESR capacitors and
increasing the value of the L
these conditions.
Note:
* denotes external components
Signal Transmission
In Normal Active and Reverse Polarity states, the AC line current is sensed across the internal resistors, R
Transmission Block Diagram, on page
through a high pass filter (with a nominal 13 Hz corner frequency), implemented using an on-chip 8 kΩ nominal resistor and an
external C
AC metallic component of the line voltage. Additionally, the signal transmission block receives the analog signal from the
Le78D11 VoSLAC device. The analog signal is amplified and sent to the line.A proportion of the signal at V
to the line.
There are three parameters which define the AC characteristics of the Le77D11 VoSLIC device. First is the input impedance
presented to the line or two-wire side (Z
third is the gain from the two-wire side to the four-wire (V
Input Impedance (Z
Z
2WIN
R
RAMP
C
is the impedance presented to the line at the two-wire side, and is defined by:
I=
I=
in Active
HSi
in Ringing
*
*
800 K
800 K
15 V
8 V
HP
CHS
capacitor, is amplified, and sent to the Le78D11 VoSLAC device at the VOUT pin. The output is proportional to the
FSET
V
i
CC
BD
100 Vin
800 k
800 K
48 V
800 K
2WIN
is 180 Ω and capacitor C
VREG
)
In Active
In Ringing
V
TRIANGLE
Inside Le77D11 SLIC Device
REF
WAVE
CLAMP
1.4 V
inductor in the post filter. The power supply output is able to track the ringing waveform under
Figure 6. Switching Power Supply Block Diagram
8), summed, attenuated and converted to voltage at the CFILT pin. This voltage then goes
2WIN
+
COMPARATOR
-
), second is the gain from the four-wire (V
BD
Z
2WIN
Zarlink Semiconductor Inc.
is 27 nF to increase the switching speed and efficiency. This increases the
OUTPUT
RESET
=
OUT
LATCH
2R
) side (G
REG
F
7
+
K
. The capacitance is sized to permit more rapid charging of the
V
SET
K
OUT
24
).
R
BLANKING
LEADING
FILTER
IMT
EDGE
DRIVER
Selectable via the Le78D11 device
10% High Duty Cycle
85.3 kHz or 256 kHz
V
SW
IN
) to the two-wire (V
+
-
0.28
CHCLK
VREG
V
+
-
VSW
ILS
SD
i
i
i
R
C
LIMi
BDi
C
VREGi
V
*
R
*
SW
BDi
* C
*
D
BGND
+
-
L
VREGi
D2
Q
SWi
S
OUT
AB
*
SWi
BGND
*
C
(see
*
FL
) side (G
SW
*
L
is also fed back
VREGi
and C
C
Figure 7,
*
D
FLi
BGND
C
SWi
BGND
*
C
SWi
ESRi
*
VREG
42
*
BGND
*
), and
use