MT90820AL Zarlink, MT90820AL Datasheet - Page 5

• Manufacturer Part Number: MT90820AL
• Description: Switch Fabric 2K x 2K/1K x 1K/512 x 512 131.072Mbps 5V 100-Pin MQFP Tray
• Manufacturer: Zarlink

Specifications of MT90820AL

• Package: 100MQFP
• Number Of Ports: 16
• Fabric Size: 2K x 2K|1K x 1K|512 x 512
• Switching Bandwidth: 131.072 Mbps
• Switch Core: Non-Blocking
• Port Speed: 2.048|4.096|8.192 Mbps
• Operating Supply Voltage: 5 V

Pin Description
41 - 48
55 - 62
65 - 72
PLCC
84
39
40
49
50
51
52
53
73
74
Pin #
MQFP
14-21
32-39
42-49
100
12
13
22
23
24
25
26
50
55
R/W / WR
AS/ALE
A0 - A7
AD0 - 7
RESET
D8 - 15
DS/RD
WFPS
Name
CSTo
DTA
CS
IM
Device Reset (Schmitt Trigger Input): This input (active LOW) puts the MT90820 in
its reset state that clears the device internal counters, registers and brings STo0 - 15 and
microport data outputs to a high impedance state. The time constant for a power up reset
circuit must be a minimum of five times the rise time of the power supply. In normal
operation, the RESET pin must be held low for a minimum of 100 nsec to reset the
device.
Wide Frame Pulse Select (Input): When 1, enables the wide frame pulse (WFP) Frame
Alignment interface. When 0, the device operates in ST-BUS/GCI mode.
Address 0 - 7 (Input): When non-multiplexed CPU bus operation is selected, these lines
provide the A0 - A7 address lines to the internal memories.
Data Strobe / Read (Input): For multiplexed bus operation, this input is DS. This active
high DS input works in conjunction with CS to enable the read and write operations.
For Motorola non-multiplexed CPU bus operation, this input is DS. This active low input
works in conjunction with CS to enable the read and write operations.
For multiplexed bus operation, this input is RD. This active low input sets the data bus
lines (AD0-AD7, D8-D15) as outputs.
Read/Write / Write (Input): In the cases of Motorola non-multiplexed and multiplexed
bus operations, this input is R/W. This input controls the direction of the data bus lines
(AD0 - AD7, D8-D15) during a microprocessor access.
For multiplexed bus operation, this input is WR. This active low input is used with RD to
control the data bus (AD0 - 7) lines as inputs.
Chip Select (Input): Active low input used by a microprocessor to activate the
microprocessor port of MT90820.
Address Strobe or Latch Enable (Input): This input is used if multiplexed bus
operation is selected via the IM input pin. For Motorola non-multiplexed bus operation,
connect this pin to ground. This pin is pulled low by an internal pull-down when not
driven.
CPU Interface Mode (input): When IM is high, the microprocessor port is in the
multiplexed mode. When IM is low, the microprocessor port is in non-multiplexed mode.
This pin is pulled low by an internal pull-down when not driven.
Address/Data Bus 0 to 7 (Bidirectional): These pins are the eight least significant data
bits of the microprocessor port. In multiplexed mode, these pins are also the input address
bits of the microprocessor port.
Data Bus 8-15 (Bidirectional): These pins are the eight most significant data bits of the
microprocessor port.
Data Transfer Acknowledgement (Active Low Output): Indicates that a data bus
transfer is complete. When the bus cycle ends, this pin drives HIGH and then tri-states,
allowing for faster bus cycles with a weaker pull-up resistor. A pull-up resistor is required
to hold a HIGH level when the pin is tri-stated.
Control Output (Output). This is a 4.096, 8.192 or 16.384 Mb/s output containing 512,
1024 or 2048 bits per frame respectively. The level of each bit is determined by the CSTo
bit in the connection memory. See External Drive Control Section.
Zarlink Semiconductor Inc.
MT90820
5
Description
Data Sheet