MT90826AL Zarlink, MT90826AL Datasheet - Page 11
![no-image](/images/manufacturer_photos/0/7/726/zarlink_sml.jpg)
MT90826AL
Manufacturer Part Number
MT90826AL
Description
Switch Fabric 4K x 4K/2K x 2K/1K x 1K 3.3V 160-Pin MQFP Tray
Manufacturer
Zarlink
Datasheet
1.MT90826AL.pdf
(46 pages)
Specifications of MT90826AL
Package
160MQFP
Number Of Ports
32
Fabric Size
4K x 4K|2K x 2K|1K x 1K
Switch Core
Non-Blocking
Port Speed
2.048|4.096|8.192|16.384 Mbps
Operating Supply Voltage
3.3 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT90826AL
Manufacturer:
ZARLINK
Quantity:
1 500
Company:
Part Number:
MT90826AL
Manufacturer:
MITEL
Quantity:
329
Company:
Part Number:
MT90826AL1
Manufacturer:
ZARLINK
Quantity:
850
Pin Description (continued)
Pin # MQFP
102-105
126-129
137-140
107-110
122,123
131-134
142-145
113-116
118,119
67-70
78,79
82,83
91-94
61-64
72-75
85-88
96-99
44
46
47
50
51
52
55
56
57
58
59
D13,C13,D12,C12
F13,F12,E13,E12
G11,F11,E11,D11
A11,B11,A10,B10
C11,C10,C9,C8
Pin # PBGA
G1,G2,H1,H2
C7,C6,C5,C4
D2,C2,C1,D1
A7,B7,A6,B6
A5,B5,A4,B4
A2,B2,A1,B1
B9,A9,B8,A8
E2,F2,E1,F1
B13,A13
A12,B12
D3,C3
A3,B3
K12
K10
K13
L12
L13
H13
H12
G13
G12
J13
K9
G10,F10,D10,E10
D12,C12,D11,C11
F11,F12,E12,E11
B10,A10,B9,A9
C10,C9,C8,D8
Pin # LBGA
A6,A5,B6,B5,
D2,C2,C1,D1
C7,C6,C5,C4
F3,G3,G1,G2
C3,D3,E4,E3
A4,A3,B4,B3
B8,A8,A7,B7
E2,E1,F1,F2
B12,A12
B11,A11
A2,B2
B1,A1
K12
H10
L12
H12
G12
G11
J11
J12
H11
H9
G9
Zarlink Semiconductor Inc.
MT90826
11
STi12-15/FEi12-15
STi16-19/FEi16-19
STi20-23/FEi20-23
STi24-27/FEi24-27
STi28-31/FEi28-31
STi10-11/FEi10-11
STo20, STo21
STo22, STo23
STi4-7/FEi4-7
STi8-9/FEi8-9
STo12 - 15
STo16 - 19
STo24 - 27
STo28 - 31
STi0/FEi0,
PLLGND
STi1/FEi1
STi2/FEi2
STi3/FEi3
PLLVDD
STo8 - 11
STo0 - 3
STo4 - 7
Name
ODE
CLK
IC2
IC3
F0i
Internal Connection 2 (3.3 V Input
with internal pull-down). Connect to
V
Internal Connection 3 (3.3 V Input
with internal pull-down). Connect to
V
Master Frame Pulse (5 V Tolerant
Input). This input accepts a 122 ns or
60 ns wide negative frame pulse. The
CPLL bit in the control register
determines the usage of the frame
pulse width. See Table 6 for details.
Phase Lock Loop Ground.
Phase Lock Loop Power Supply.
3.3 V
Master Clock (5 V Tolerant Input).
Serial clock for shifting data in/out on
the serial streams. This pin accepts a
clock frequency of 8.192 MHz or
16.384 MHz. The CPLL bit in the
control register determines the usage
of the clock frequency. See Table 6 for
details.
Output Drive Enable (5 V Tolerant
Input). This is the output-enable
control pin for the STo0 to STo31 serial
outputs. See Table 2 for details.
Serial Input Streams 0 to 31 and
Frame Evaluation Inputs 0 to 31 (5 V
Tolerant Inputs). Serial data input
streams. These streams may have
data rates of 2.048, 4.096, 8.192 or
16.384 Mbps, depending upon the
value programmed at bits DR0 - DR2 in
the control register. In the frame
evaluation mode, they are used as the
frame evaluation inputs.
ST-BUS Output 0 to 31 (Three-state
Outputs). Serial data output streams.
These streams may have data rates of
2.048, 4.096, 8.192, or 16.384 Mbps,
depending upon the value programmed
at bits DR0 - DR2 in the control
register.
SS
SS
for normal operation.
for normal operation.
Description
Data Sheet