72821L25TF Integrated Device Technology (Idt), 72821L25TF Datasheet - Page 8

• Manufacturer Part Number: 72821L25TF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72821L25TF

• Package: 64STQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 1Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

LOW when the amount of data in Array A (B) reaches the almost-full condition.
If no reads are performed after Reset, PAFA (PAFB) will go LOW after (256-m)
writes to the IDT72801's FIFO A (B); (512-m) writes to the IDT72811's FIFO
A (B); (1,024-m) writes to the IDT72821's FIFO A (B); (2,048-m) writes to the
IDT72831's FIFO A (B); (4,096-m) writes to the IDT72841's FIFO A (B); or
(8,192-m) writes to the IDT72851's FIFO A (B).
Write Clock WCLKA (WCLKB). The offset “m” is defined in the Full Offset
registers.
of WCLKA (WCLKB).
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
Programmable Almost–Full Flag (PAFA, PAFB) — PAFA (PAFB) will go
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of the
If there is no Full offset specified, PAFA (PAFB) will go LOW at Full-7 words.
PAFA (PAFB) is synchronized with respect to the LOW-to-HIGH transition
(n+1) to (256-(m+1))
(n+1) to (2,048-(m+1))
(2,048-m)
(256-m)
1 to n
72801
1 to n
256
72831
2,048
0
(2)
(2)
0
(1)
to 255
(1)
to 2,047
NUMBER OF WORDS IN ARRAY B
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY A
NUMBER OF WORDS IN ARRAY B
(n+1) to (4,096-(m+1))
(4,096-m)
(n+1) to (512-(m+1))
(512-m)
1 to n
72841
1 to n
4,096
72811
512
(2)
0
0
(2)
(1)
to 4,095
(1)
to 511
(n+1) to (1,024-(m+1))
(n+1) to (8,192-(m+1))
(1,024-m)
(8,192-m)
TM
1 to n
72821
1 to n
1,024
8
72851
8,192
0
(2)
go LOW when the read pointer is "n+1" locations less than the write pointer. The
offset "n" is defined in the Empty Offset registers. If no reads are performed after
Reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B).
words.
of the Read Clock RCLKA (RCLKB).
outputs for memory array A, QB
array B
(2)
0
(1)
to 1,023
(1)
Programmable Almost–Empty Flag (PAEA, PAEB) — PAEA (PAEB) will
If there is no Empty offset specified, PAEA (PAEB) will go LOW at Empty+7
PAEA (PAEB) is synchronized with respect to the LOW-to-HIGH transition
Data Outputs (QA
to 8,191
.
0
FFA
FFA
FFB
FFB
FFA
FFA
FFB
FFB
FFA
FFA
FFA
FFB
FFB
FFB
FFA
FFA
FFA
FFB
FFB
FFB
– QA
H
H
H
H
H
H
H
H
L
L
8,
QB
0
- QB
0
– QB
PAFA
PAFA
PAFA
PAFA
PAFA
PAFB
PAFB
PAFB
PAFB
PAFB
PAFA
PAFA
PAFA
PAFA
PAFA
PAFB
PAFB
PAFB
PAFB
PAFB
8
are the nine data outputs for memory
COMMERCIAL AND INDUSTRIAL
H
H
H
H
H
H
L
L
L
L
8
) — QA
TEMPERATURE RANGES
PAEA
PAEA
PAEA
PAEA
PAEA
PAEB
PAEB
PAEB
PAEB
PAEB
PAEA
PAEA
PAEA
PAEA
PAEA
PAEB
PAEB
PAEB
PAEB
PAEB
0
JANUARY 13, 2009
- QA
H
H
H
H
H
L
L
H
L
L
8
are the nine data
EFA
EFA
EFA
EFA
EFA
EFB
EFB
EFB
EFB
EFB
EFA
EFA
EFA
EFA
EFA
EFB
EFB
EFB
EFB
EFB
H
H
H
H
H
H
H
H
L
L