XC2V4000-4FF1152C Xilinx Inc, XC2V4000-4FF1152C Datasheet - Page 55

• Manufacturer Part Number: XC2V4000-4FF1152C
• Description: FPGA Virtex-II Family 4M Gates 51840 Cells 650MHz 0.15um/0.12um (CMOS) Technology 1.5V 1152-Pin FCBGA
• Manufacturer: Xilinx Inc

Specifications of XC2V4000-4FF1152C

• Package: 1152FCBGA
• Family Name: Virtex-II
• Device Logic Units: 51840
• Device System Gates: 4000000
• Number Of Registers: 46080
• Maximum Internal Frequency: 650 MHz
• Typical Operating Supply Voltage: 1.5 V
• Maximum Number Of User I/os: 824
• Ram Bits: 2211840
• Re-programmability Support: Yes
• Case: BGA
• Dc: 05+

Virtex-II Performance Characteristics
This section provides the performance characteristics of
some common functions and designs implemented in
Virtex-II devices. The numbers reported here are worst-case
values; they have all been fully characterized. Note that
these values are subject to the same guidelines as
Switching Characteristics, page 9
Table 11: Pin-to-Pin Performance
Table 12
Table 12: Register-to-Register Performance
DS031-3 (v3.5) November 5, 2007
Product Specification
Basic Functions
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Combinatorial (pad to LUT to pad)
Memory
Block RAM
Pad to setup
Clock to Pad
Distributed RAM
Pad to setup
Clock to Pad
Basic Functions
16-bit Address Decoder
32-bit Address Decoder
64-bit Address Decoder
4:1 MUX
8:1 MUX
16:1 MUX
32:1 MUX
Register to LUT to Register
shows internal (register-to-register) performance. Values are reported in MHz.
R
Description
Description
(speed files).
Device Used & Speed Grade
Virtex-II
Device Used & Speed
www.xilinx.com
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
Virtex-II Platform FPGAs: DC and Switching Characteristics
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
XC2V1000 -5
Grade
Table 11
including IOB delays; that is, delay through the device from
input pin to output pin. In the case of multiple inputs and out-
puts, the worst delay is reported.
provides pin-to-pin values (in nanoseconds)
Register-to-Register
Pin-to-Pin (with I/O delays)
Performance
5.1 (no clk skew)
398
291
274
563
454
414
323
613
6.3
7.7
9.3
5.7
6.5
6.7
8.7
5.0
1.6
9.5
2.7
Module 3 of 4
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7