954204BGLFT Integrated Device Technology (Idt), 954204BGLFT Datasheet - Page 14

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954204BGLFT

Manufacturer Part Number
954204BGLFT
Description
PLL Clock Synthesizer Dual 56-Pin TSSOP T/R
Manufacturer
Integrated Device Technology (Idt)
Type
PLL Clock Synthesizerr
Datasheet

Specifications of 954204BGLFT

Package
56TSSOP
Number Of Elements Per Chip
2
Output Frequency Range
33.33 to 400 MHz
Operating Temperature
0 to 70 °C
Operating Supply Voltage
3.3 V
CLKREQ# - Assertion (transition from logic “1” to logic “0”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become active per the timing found in
Table 4. The clock will become active in a glitch free manner, providing a full cycle at the time it becomes active.
CLKREQ# - De-Assertion (transition from logic “0” to logic “1”)
The impact of asserting the CLKREQ# pin is that the SRCCLK output will become inactive setliing in the Tristate
condition per the timing found in Table 4. The clock will become inactive in a glitch free manner.
0933D—03/16/05
1
Table 3. Power-Up CLKREQ# Timing
Table 4. CLKREQ# Control Timing
This timing is valid only after system clocks are stable.
T
Symbol
Symbol
T
T
T
SRCSTBL
PVCRL
CRHoff
CRHon
Integrated
Circuit
Systems, Inc.
CLKREQ#
V
SRCCLK
PCIEXDEV
SRC Clock Stablilzation Time from assertion
CLKREQ#
CLKREQ# De-asserted High to SRCCLK
Power Valid to CLKREQ# Output Active
CLKREQ# Asserted LOW to SRCCLK
SRCCLK
of CLKREQ# (Fig. 1)
Parked (Fig. 2)
Active (Fig. 2)
Parameter
Parameter
(Fig. 1)
Figure 1. Power-Up CLKREQ# Timing
Figure 2. CLKREQ# Control Timing
1
T
PVCRL
14
Power Stable to Device
T
SRCSTBL
Min
Min
0
Max
Max
100
800
0.4
Units
Units
ICS954204
µs
µs
µs
µs

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