89TTM552BL Integrated Device Technology (Idt), 89TTM552BL Datasheet - Page 9

• Manufacturer Part Number: 89TTM552BL
• Description: ATM Traffic Management 10Gbps 1.8V 1192-Pin FCBGA
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 89TTM552BL

• Package: 1192FCBGA
• Traffic Class: VBR
• Throughput: 10000 Mbps
• Typical Operating Supply Voltage: 1.8 V
• Minimum Operating Supply Voltage: 1.71 V
• Maximum Operating Supply Voltage: 1.89 V

IDT 89TTM552
DRAM0_CKE
DRAM0_CS_N
DRAM0_D[71:0]
DDAM0_DQS[8:0]
DRAM0_RAS_N
DRAM0_WE_N
DRAM1_ADDR[12:0]
DRAM1_BNK[1:0]
DRAM1_CAS_N
DRAM1_CKE
DRAM1_CS_N
DRAM1_D[71:0]
DDAM1_DQS[8:0]
DRAM1_RAS_N
DRAM1_WE_N
DRAM_VREF[7:0]
STAT_ARR[17:0],
STAT_ARR_PRTY
STAT_DEP[12:0],
STAT_DEP_PRTY
STAT_CLK
STAT_TIC
STAT_VREF
1.
Note that the PIC buffer interface requires a 2.6V power supply. That means, separate power supplies are needed for the NPU/System Rx & Tx (LVDS)
interfaces and the PIC buffer (SSTL2) interface.
Signal Name
Signal Name
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
2.6V SSTL2 CMOS
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
1.5V HSTL Class 1
I/O Type
I/O Type
0.75V
1.3V
Table 7 PIC Buffer (DDR SDRAM) (Part 2 of 2)
Table 8 Statistics Interface
Dir.
Dir.
—
O
O
B
B
O
O
O
O
O
O
O
B
B
O
O
O
O
O
O
I
175 / 5 MHz Statistic port cell time tick to external statistic controller device
9 of 37
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
175 MHz
Freq.
Freq.
—
—
—
—
—
—
—
—
Group 0 clock enable
Group 0 chip select (active low)
Group 0 data
Group 0 DDR data strobes: Output with write data, input with
read data
Group 0 row address strobe (active low)
Group 0 write enable (active low)
Group 1 SDRAM address
Group 1 SDRAM bank address
Group 1 column address strobe (active low)
Group 1 clock enable
Group 1 chip select (active low)
Group 1 data
Group 1 DDR data strobes: Output with write data, input with
read data
Group 1 row address strobe (active low)
Group 1 write enable (active low)
Arrival statistics port data and parity
Departure statistics port data and parity
Source-synchronous statistic port clock to external statistic
controller device
HSTL reference. Nominally V
SSTL_2 reference voltage. Connect to (Vddq/2) 1.3 volts.
Remarks
Remarks
DDQ
/ 2, so connect to 0.75 V
April 7, 2005