72841L15PF Integrated Device Technology (Idt), 72841L15PF Datasheet - Page 14

• Manufacturer Part Number: 72841L15PF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72841L15PF

• Package: 64TQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 4Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

OPERATING CONFIGURATIONS
Device Configuration, the Read Enable 2 RENA2 (RENB2) control input
creased simply by connecting the corresponding input control signals of
FIFOs A and B. A composite flag should be created for each of the endpoint
status flags EFA and EFB, also FFA and FFB). The partial status flags
PAEA, PAFB, PAEA and PAFB can be detected from any one device.
Figure 15 demonstrates an 18-bit word width using the two FIFOs contained
in one IDT72801/72811/72821/72831/72841/72851. Any word width can
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
SINGLE DEVICE CONFIGURATION — When FIFO A (B) is in a Single
WIDTH EXPANSION CONFIGURATION — Word width may be in-
FULL FLAG
DATA IN
WRITE CLOCK
WRITE ENABLE
WRITE ENABLE/LOAD
18
Figure 14. Block Diagram of One of the IDT72801/72811/72821/72831/72841/72851's two FIFOs
WENA2/LDA (WENB2/LDB)
Figure 15. Block diagram of the two FIFOs contained in one IDT72801/72811/
9
DA
72821/72831/72841/72851 configured for an 18-bit width-expansion
WENA2/LDA
0
FFB
DA0 - DA8
WCLKA
WENA1
FFA
WENA1 (WENB1)
WCLKA (WCLKB)
- DA
PAFA (PAFB)
8
(DB
FFA (FFB)
0
- DB
RSA
1,024x9
2,048x9
4,096x9
8,192x9
ARRAY
512x9
256x9
RAM
configured as a single device
8
)
A
RENA2
9
DB0 - DB8
RENA1
OEA1
RCLKA
2WENB2/LDB
TM
WCLKB
14
72801
72811
72821
72831
72841
72851
WENB1
FIFO
A (B)
IDT
QA0 - QA8
can be grounded (see Figure 14). In this configuration, the Write Enable 2/
Load WENA2/LDA (WENB2/LDB) pin is set LOW at Reset so that the pin
operates as a control to load and read the programmable flag offsets.
be attained by adding additional IDT72801/72811/72821/72831/72841/
72851s.
Enable 2 (RENA2 and RENB2) control inputs can be grounded (see
Figure 15). In this configuration, the Write Enable 2/Load (WENA2/LDA,
WENB2/LDB) pins are set LOW at Reset so that the pin operates as a
control to load and read the programmable flag offsets.
RSA (RSB)
RENA2 (RENB2)
When these devices are in a Width Expansion Configuration, the Read
RSB
9
1,024x9
2,048x9
4,096x9
8,192x9
ARRAY
512x9
256x9
RAM
B
RENB2
RCLKA (RCLKB)
RENA1 (RENB1)
OEA (OEB)
QA
EFA (EFB)
PAEA (PAEB)
0
QB0 - QB8
RENB1
RCLKB
OEB
- QA
8
EFA
EFB
(QB
0
- QB
8
)
COMMERCIAL AND INDUSTRIAL
9
TEMPERATURE RANGES
READ CLOCK
EMPTY FLAG
READ ENABLE
OUTPUT ENABLE
RESET
18
JANUARY 13, 2009
DATA OUT
3034 drw 16
3034 drw 15