CS5102A-JL Cirrus Logic Inc, CS5102A-JL Datasheet - Page 4
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CS5102A-JL
Manufacturer Part Number
CS5102A-JL
Description
ADC Single SAR 20KSPS 16-Bit Serial 28-Pin PLCC
Manufacturer
Cirrus Logic Inc
Datasheet
1.CS5101A-KL8.pdf
(40 pages)
Specifications of CS5102A-JL
Package
28PLCC
Resolution
16 Bit
Sampling Rate
20 KSPS
Architecture
SAR
Number Of Adcs
1
Number Of Analog Inputs
2
Digital Interface Type
Serial
Input Type
Voltage
Signal To Noise Ratio
90(Typ) dB
Polarity Of Input Voltage
Unipolar|Bipolar
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Manufacturer
Quantity
Price
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Manufacturer:
Cirrus Logic Inc
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SWITCHING CHARACTERISTICS
VA-, VD- = -5V
Notes: 13. External loading capacitors are required to allow the crystal to oscillate. Maximum crystal frequency
4
CLKIN Period
CLKIN Low Time
CLKIN High Time
Crystal Frequency
SLEEP Rising to Oscillator Stable
RST Pulse Width
RST to STBY Falling
RST Rising to STBY Rising
CH1/2 Edge to TRK1, TRK2 Rising
CH1/2 Edge to TRK1, TRK2 Falling
HOLD to SSH Falling
HOLD to TRK1, TRK2, Falling
HOLD to TRK1, TRK2, SSH Rising
HOLD Pulse Width
HOLD to CH1/2 Edge
HOLD Falling to CLKIN Falling
14. With a 8 MHz crystal, two 10 pF loading capacitors and a 10 M
15. These times are for FRN mode.
16. SSH only works correctly if HOLD falling edge is within +15 to +30 ns of CH1/2 edge or if CH1/2 edge
17. When HOLD goes low, the analog sample is captured immediately. To start conversion, HOLD must
is 8.0 MHz in FRN mode (100 kHz sample rate).
occurs after HOLD rises to 64 t
be latched by a falling edge of CLKIN. Conversion will begin on the next rising edge of CLKIN after
HOLD is latched. If HOLD is operated synchronous to CLKIN, the HOLD pulse width may be as
narrow as 150 ns for all CLKIN frequencies if CLKIN falls 95 ns after HOLD falls. This
ensures that the HOLD pulse will meet the minimum specification for t
10%; Inputs: Logic 0 = 0V, Logic 1 = VD+; C
Parameter
clk
after HOLD has fallen. These times are for PDT and RBT modes.
(T
(Note 13)
(Note 14)
(Note 15)
(Note 15)
(Note 16)
(Note 16)
(Note 16)
(Note 17)
(Note 16)
(Note 17)
A
(Note 4)
= T
MIN
-16
-16
-8
-8
to T
Symbol
L
t
t
t
t
t
t
t
t
t
drsh1
dfsh4
dfsh2
dfsh1
f
f
t
t
drsh
t
t
t
hold
dhlri
clkh
t
drrs
MAX
= 50 pF)
xtal
xtal
clkl
cal
hcf
clk
clk
rst
-
; VA+, VD+ = 5V
1t
66t
37.5
37.5
clk
Min
108
250
150
2.0
2.0
15
95
-
-
-
-
-
-
-
parallel resistor (see Figure 8).
+20
clk
hcf
11,528,160
.
Typ
100
120
80
60
2
-
-
-
-
-
-
-
-
-
-
-
-
10%;
68t
68t
CS5101A
1tclk+10
10,000
10,000
9.216
63t
64t
Max
clk
clk
4.0
-
-
-
-
-
-
-
-
+260
+260
clk
clk
DS45F2
Units
MHz
MHz
ms
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clk