MAX4998ETI+T Maxim Integrated Products, MAX4998ETI+T Datasheet - Page 3

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MAX4998ETI+T

Manufacturer Part Number
MAX4998ETI+T
Description
IC DISPLAY PORT MUX 2CH 28-TQFN
Manufacturer
Maxim Integrated Products
Series
DisplayPort™r
Datasheet

Specifications of MAX4998ETI+T

Function
Switch
Circuit
3 x DPDT, 1 x SPDT
On-state Resistance
7 Ohm
Voltage Supply Source
Single Supply
Voltage - Supply, Single/dual (±)
3.3V
Current - Supply
500µA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Note 3: All units are 100% production tested at T
Note 4: DR
Note 5: Guaranteed by design. Not production tested.
Note 6: Flatness is defined as the difference between the maximum and minimum value of on-resistance as measured over the
ELECTRICAL CHARACTERISTICS (continued)
(V
noted.) (Note 3)
Figure 1. Switching Time
SEL1 and SEL2 to Switch
Turn-Off Time
Differential Insertion Loss
Differential Crosstalk
Differential Return Loss
Signal Data Rate
Differential -3dB Bandwidth
Differential Off-Isolation
LOGIC INPUT (SEL1, SEL2)
Input Logic-High
Input Logic-Low
Input Logic Hysteresis
Input Leakage Current
POWER SUPPLY
Power-Supply Range
V
DD
DD
= +3.3V Q10%, T
Supply Current
Two-Lane and Four-Lane DisplayPort Passive
design and characterization and are not production tested.
specified analog signal range.
LOGIC
PARAMETER
INPUT
SEL
ON
V
= R
N_
Switches with Separate AUX/HPD Control
ON(MAX)
C
V
_______________________________________________________________________________________
OUT
L
INCLUDES FIXTURE AND STRAY CAPACITANCE.
NO_ OR NC_
SEL_
MAX4998/MAX14998
A
= V
GND
= T
N_
(
- R
MIN
R
L
R
+ R
ON(MIN)
L
to T
ON
)
+3.3V
MAX,
S
V
SYMBOL
DD
t
DD21_OFF
S
OFF_SEL
S
S
V
.
DDCTK
f
COM_
-3BW
V
DD21
DD11
HYST
I
V
BR
V
I
DD
IN
DD
unless otherwise noted. Typical values are at V
IH
IL
A
R
L
= +85NC. Limits over the operating temperature range are guaranteed by
V
C
f = 0.8GHz (Figure 2)
f = 1.35GHz (Figure 2)
f = 0.8GHz (Figure 2)
f = 1.35GHz (Figure 2)
f = 0.8GHz (Figure 2)
f = 1.35GHz (Figure 2)
R
R
f = 1.35GHz (Figure 2)
V
V
NO_
SEL_
SEL_
L
S
S
= 100pF (Figure 1)
= R
= R
or V
= 0V or V
= 0V or V
L
L
C
L
= 100I balanced
= 100I balanced
V
NC_
OUT
CONDITIONS
= +1.0V, R
DD
DD
SWITCH
OUTPUT
SWITCH
OUTPUT
LOGIC
COM_
COM_
INPUT
SEL_
Test Circuits/Timing Diagrams
L
= 50I,
V
V
0V
0V
IH
IL
DD
V
= +3.3V, T
50%
OUT
MIN
1.4
3.0
-1
0.9 x V
0.9 x V
t
t
OFF_SEL
ON_SEL
OUT
OUT
A
-0.67
-0.95
= +25NC, unless otherwise
TYP
100
500
-37
-34
-20
-14
-28
8.5
17
5
t
t
r
f
0.9 x V
< 5ns
< 5ns
MAX
0.9 x V
850
0.5
3.6
50
+1
t
OFF_SEL
t
ON_SEL
OUT
OUT
UNITS
Gbps
GHz
mV
dB
dB
dB
dB
FA
FA
ns
V
V
V
3

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