LFE2-6SE-6TN144I Lattice, LFE2-6SE-6TN144I Datasheet - Page 2
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LFE2-6SE-6TN144I
Manufacturer Part Number
LFE2-6SE-6TN144I
Description
IC FPGA 6KLUTS 144TQFP
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2-6SE-6TN144I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-6SE-6TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 2 of 385
- Download datasheet (3Mb)
June 2008
Features
■ High Logic Density for System Integration
■ Embedded SERDES (LatticeECP2M Only)
■ sysDSP™ Block
■ Flexible Memory Resources
■ sysCLOCK Analog PLLs and DLLs
Table 1-1. LatticeECP2 (Including “S-Series”) Family Selection Guide
© 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand
or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
LUTs (K)
Distributed RAM (Kbits)
EBR SRAM (Kbits)
EBR SRAM Blocks
sysDSP Blocks
18x18 Multipliers
GPLL + SPLL + DLL
Maximum Available I/O
Packages and I/O Combinations
144-pin TQFP (20 x 20 mm)
208-pin PQFP (28 x 28 mm)
256-ball fpBGA (17 x 17 mm)
484-ball fpBGA (23 x 23 mm)
672-ball fpBGA (27 x 27 mm)
900-ball fpBGA (31 x 31 mm)
• 6K to 95K LUTs
• 90 to 583 I/Os
• Data Rates 250 Mbps to 3.125 Gbps
• Up to 16 channels per device
• 3 to 42 blocks for high performance multiply and
• Each block supports
• 55Kbits to 5308Kbits sysMEM™ Embedded
• 12K to 202Kbits distributed RAM
• Two GPLLs and up to six SPLLs per device
• Two general purpose DLLs per device
PCI Express, Ethernet (1GbE, SGMII), OBSAI,
CPRI and Serial RapidIO.
accumulate
Block RAM (EBR)
– One 36x36, four 18X18 or eight 9X9 multipliers
– 18Kbit block
– Single, pseudo dual and true dual port
– Byte Enable Mode support
– Single port and pseudo dual port
– Clock multiply, divide, phase & delay adjust
– Dynamic PLL adjustment
Device
ECP2-6
2+0+2
190
190
12
55
12
90
6
3
3
LatticeECP2/M Family Data Sheet
ECP2-12
2+0+2
221
297
131
193
297
12
24
12
24
93
6
1-1
■ Pre-Engineered Source Synchronous I/O
■ Programmable sysI/O™ Buffer Supports
■ Flexible Device Configuration
■ Optional Bitstream Encryption
■ System Level Support
ECP2-20
2+0+2
Wide Range Of Interfaces
(LatticeECP2/M “S” Versions Only)
276
402
131
193
331
402
21
42
15
28
• DDR registers in I/O cells
• Dedicated gearing logic
• Source synchronous standards support
• Dedicated DDR and DDR2 memory support
• Dedicated DQS support
• LVTTL and LVCMOS 33/25/18/15/12
• SSTL 3/2/18 I, II
• HSTL15 I and HSTL18 I, II
• PCI and Differential HSTL, SSTL
• LVDS, RSDS, Bus-LVDS, MLVDS, LVPECL
• 1149.1 Boundary Scan compliant
• Dedicated bank for configuration I/Os
• SPI boot flash interface
• Dual boot images supported
• TransFR™ I/O for simple field updates
• Soft Error Detect macro embedded
• ispTRACY™ internal logic analyzer capability
• On-chip oscillator for initialization & general use
• 1.2V power supply
7
– SPI4.2, SFI4 (DDR Mode), XGMII
– High Speed ADC/DAC devices
– DDR1: 400 (200MHz) / DDR2: 533 (266MHz)
ECP2-35
2+0+2
332
450
331
450
32
64
18
32
8
Introduction
ECP2-50
DS1006
2+2+2
387
500
339
500
48
96
21
18
72
Data Sheet DS1006
Introduction_01.7
ECP2-70
2+4+2
1032
136
583
500
583
68
60
22
88
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