LFE2M50E-5FN672I Lattice, LFE2M50E-5FN672I Datasheet - Page 87
LFE2M50E-5FN672I
Manufacturer Part Number
LFE2M50E-5FN672I
Description
IC FPGA 48KLUTS 672FPBGA
Manufacturer
Lattice
Datasheet
1.LFE2-12E-5FN256C.pdf
(385 pages)
Specifications of LFE2M50E-5FN672I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M50E-5FN672I
Manufacturer:
LATTICE
Quantity:
47
Company:
Part Number:
LFE2M50E-5FN672I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
sysCLOCK SPLL Timing
f
f
f
f
f
AC Characteristics
t
t
t
t
t
t
t
t
t
t
t
1. Jitter sample is taken over 10,000 samples of the primary PLL output with clean reference clock and no additional I/O pins toggling.
2. Output clock is valid after t
3. Using LVDS output buffers.
4. Phase accuracy of CLKOS compared to CLKOP.
5. Value of external capacitor: 5.6 nF ±20%, NPO dielectric, ceramic chip capacitor, 1206 or smaller package, connected to PLLCAP pin.
6. f
Timing v.A 0.11
Parameter
IN
OUT
OUT2
VCO
PFD
DT
PH
OPJIT
SK
W
LOCK
IPJIT
FBKDLY
HI
LO
RST
4
OUT
2
1
(max) = f
Input Clock Frequency (CLKI, CLKFB)
Output Clock Frequency (CLKOP, CLKOS)
K-Divider Output Frequency (CLKOK)
PLL VCO Frequency
Phase Detector Input Frequency
Output Clock Duty Cycle
Output Phase Accuracy
Output Clock Period Jitter
Input Clock to Output Clock Skew
Output Clock Pulse Width
PLL Lock-in Time
Input Clock Period Jitter
External Feedback Delay
Input Clock High Time
Input Clock Low Time
RST Pulse Width (RESETM/RESETK)
Reset Signal Pulse Width (CNTRST)
IN
* 10 for f
IN
LOCK
< 5MHz.
Description
for PLL reset and dynamic delay adjustment.
Over Recommended Operating Conditions
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Without external capacitor
With external capacitor
Default Duty Cycle Selected
f
50 ≤ f
f
Divider Ratio = Integer
At 90% or 10%
Without external capacitor
With external capacitor
90% to 90%
10% to 10%
Without external capacitor
With external capacitor
OUT
OUT
3-36
≥ 100 MHz
< 50 MHz
OUT
< 100 MHz
Conditions
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
5, 6
5
5
6
5
5
3
0.258
0.039
Min.
640
500
0.5
0.5
33
33
33
45
15
20
—
—
—
—
—
—
—
—
—
2
5
2
1
Typ.
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
±0.05
0.025
Max.
1280
±125
±250
±200
0.04
420
420
420
210
420
150
500
50
25
50
55
—
10
—
—
—
—
—
Units
UIPP
UIPP
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
µs
µs
ns
ns
ns
ns
ns
µs
%
UI
ps
ps
ps
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