LFE2M100SE-7FN1152C Lattice, LFE2M100SE-7FN1152C Datasheet - Page 29
LFE2M100SE-7FN1152C
Manufacturer Part Number
LFE2M100SE-7FN1152C
Description
IC FPGA 95KLUTS 1152FPBGA
Manufacturer
Lattice
Datasheet
1.LFE2M100SE-5FN900C.pdf
(386 pages)
Specifications of LFE2M100SE-7FN1152C
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M100SE-7FN1152C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
MULTADDSUBSUM sysDSP Element
In this case, the operands A0 and B0 are multiplied and the result is added/subtracted with the result of the multi-
plier operation of operands A1 and B1. Additionally the operands A2 and B2 are multiplied and the result is added/
subtracted with the result of the multiplier operation of operands A3 and B3. The result of both addition/subtraction
are added in a summation block. The user can enable the input, output and pipeline registers. Figure 2-26 shows
the MULTADDSUBSUM sysDSP element.
Figure 2-26. MULTADDSUBSUM
Clock, Clock Enable and Reset Resources
Global Clock, Clock Enable and Reset signals from routing are available to every DSP block. Four Clock, Reset
and Clock Enable signals are selected for the sysDSP block. From four clock sources (CLK0, CLK1, CLK2, CLK3)
Multiplicand A0
Multiplicand A1
Multiplicand A2
Multiplicand A3
Multiplier B0
Multiplier B1
Multiplier B2
Multiplier B3
Signed A
Signed B
Shift Register B Out
Addn0
Addn1
Shift Register B In
n
n
n
n
Register B
Register B
Register B
Register B
Input Data
Input Data
Input Data
Input Data
n
n
n
n
n
n
n
n
n
Register
Register
Register
Register
Input
Input
Input
Input
m
m
m
m
Input Data
Register A
Input Data
Register A
Input Data
Register A
Input Data
Register A
m
m
m
m
m
Shift Register A Out
Shift Register A In
m
m
m
m
Register
Register
Register
Register
Pipeline
Pipeline
Pipeline
Pipeline
m
n
n
n
m
n
m
n
2-26
Multiplier
Multiplier
Multiplier
Multiplier
To Add/Sub1
To Add/Sub0, Add/Sub1
To Add/Sub0, Add/Sub1
To Add/Sub0
Pipeline
Register
Pipeline
Register
x
x
x
x
Register
Register
Pipeline
Pipeline
(default)
(default)
m+n
m+n
(default)
(default)
m+n
m+n
Add/Sub0
Add/Sub1
LatticeECP2/M Family Data Sheet
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
m+n+1
m+n+1
SUM
m+n+2
m+n+2
Architecture
Output
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