PIC16LF1938-I/MV Microchip Technology, PIC16LF1938-I/MV Datasheet
PIC16LF1938-I/MV
Specifications of PIC16LF1938-I/MV
Related parts for PIC16LF1938-I/MV
PIC16LF1938-I/MV Summary of contents
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... LCD Driver and nanoWatt XLP Technology 2011 Microchip Technology Inc. PIC16(L)F1938/9 28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Preliminary Data Sheet DS41574A ...
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... PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver with nanoWatt XLP Technology Devices Included In This Data Sheet: • PIC16F1938 • PIC16LF1938 • PIC16F1939 • PIC16LF1939 Other PIC16(L)F193X Devices Available: • PIC16(L)F1933 (DS41575) • PIC16(L)F1934/6/7 (DS41364) PIC16(L)F193X devices referred to in this Note: data sheet apply only to PIC16(L)F1938/9 ...
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... Software enable hysteresis • Voltage Reference Module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection PIC16(L)F193X Family Types PIC16F1938 16384 256 1024 PIC16LF1938 PIC16F1939 16384 256 1024 PIC16LF1939 DS41574A-page ...
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... SEG2/CLKIN/OSC1/RA7 CAP (2) SEG1/V /CLKOUT/OSC2/RA6 (1) P2B /T1CKI/T1OSO/RC0 (1) (1) P2A /CCP2 /T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 Pin function is selectable via the APFCON register. Note 1: PIC16F1938 devices only. 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 PIC16F1938, PIC16LF1938) ( RB7/ICSPDAT/ICDDAT/SEG13 28 1 RB6/ICSPCLK/ICDCLK/SEG14 27 2 RB5/AN13/CPS5/P2B RB4/AN11/CPS4/P1D/COM0 4 RB3/AN9/C12IN2-/CPS3/CCP2 RB2/AN8/CPS2/P1B/VLCD2 6 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 ...
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... REF SEG15/COM3/V +/C1IN+/AN3/RA3 REF SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4 (1) (2) (1) (1) SEG5 /V /SS /SRNQ/CPS7/C2OUT /AN4/RA5 CAP SEG2/CLKIN/OSC1/RA7 (2) SEG1/V /CLKOUT/OSC2/RA6 CAP Pin function is selectable via the APFCON register. Note 1: PIC16F1938 devices only. 2: DS41574A-page 6 PIC16F1938, PIC16LF1938 PIC16F1938 4 18 PIC16LF1938 RC7/RX/DT/P3B/SEG8 15 Preliminary (1) (1) RB3/AN9/C12IN2-/CPS3/CCP2 ...
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... DD Vss 8, 5, — — — Pin functions can be moved using the APFCON register. Note 1: PIC16F1938 devices only. 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 , PIC16LF1938) — — — (1) SRNQ (1) — — — — — — — — — — — — ...
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... PIC16F1939 devices only. 2: DS41574A-page /AN4/RA5 7 34 /AN5/RE0 Preliminary RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 (1) (1) (1) RB5/AN13/CPS5/CCP3 /P3A /T1G /COM1 RB4/AN11/CPS4/COM0 RB3/AN9/C12IN2-/CPS3/CCP2 (1) (1) /P2A /VLCD3 RB2/AN8/CPS2/VLCD2 RB1/AN10/C12IN3-/CPS1/VLCD1 RB0/AN12/CPS0/SRI/INT/SEG0 RD7/CPS15/P1D/SEG20 RD6/CPS14/P1C/SEG19 RD5/CPS13/P1B/SEG18 RD4/CPS12/P2D/SEG17 RC7/RX/DT/SEG8 RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G (1) /SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B (1) 2011 Microchip Technology Inc. ...
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... Pin Diagram – 40-Pin QFN 5X5 ( 40-pin QFN SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 SEG0/SRI/INT/CPS0/AN12/RB0 VLCD1/C12IN3-/CPS1/AN10/RB1 VLCD2/CPS2/AN8/RB2 Pin function is selectable via the APFCON register. Note 1: PIC16F1939 devices only. 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 PIC16F1939, PIC16LF1939 RC0/T1OSO/T1CKI/P2B 2 29 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN/SEG2 PIC16F1939 ...
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... Pin function is selectable via the APFCON register. Note 1: PIC16F1939 devices only. 2: DS41574A-page 10 1 RA6/OSC2/CLKOUT RA7/OSC1/CLKIN/SEG2 PIC16F1939 PIC16LF1939 7 RE2/AN7/CCP5/SEG23 27 8 RE1/AN6/P3B/SEG22 26 9 RE0/AN5/CCP3 25 10 RA5/AN4/C2OUT RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4 Preliminary (2) /SEG1 CAP (1) (1) /P3A /SEG21 (1) (1) (1) (2) /CPS7/SRNQ /SS /V /SEG5 CAP 2011 Microchip Technology Inc. ...
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... PIC16F1939, PIC16LF1939) 44-Pin TQFP ( 44-pin TQFP SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2 (1) (1) VLCD3/P2A /CPS3/C12IN2-/AN9/RB3 /CCP2 Pin function is selectable via the APFCON register. Note 1: PIC16F1939 devices only. 2: 2011 Microchip Technology Inc. PIC16(L)F1938 RC0/T1OSO/T1CKI/P2B RA6/OSC2/CLKOUT/V 3 RA7/OSC1/CLKIN/SEG2 PIC16F1939 PIC16LF1939 ...
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... SEG23 — — — — — — Y — — — — — — — — — — 2011 Microchip Technology Inc. V CAP — — — — V CAP OSC2/ CLKOUT V CAP OSC1/ CLKIN — — — — — — ...
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... Appendix A: Data Sheet Revision History.......................................................................................................................................... 439 ® Appendix B: Migrating From Other PIC Devices.............................................................................................................................. 439 Index .................................................................................................................................................................................................. 441 The Microchip Web Site ..................................................................................................................................................................... 449 Customer Change Notification Service .............................................................................................................................................. 449 Customer Support .............................................................................................................................................................................. 449 Reader Response .............................................................................................................................................................................. 450 Product Identification System ............................................................................................................................................................ 451 2011 Microchip Technology Inc. PIC16(L)F1938/9 Preliminary DS41574A-page 13 ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com DS41574A-page 14 to receive the most current information on all of our products. Preliminary 2011 Microchip Technology Inc. ...
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... Capture/Compare/PWM Modules ECCP1 ECCP2 ECCP3 CCP4 CCP5 Comparators C1 C2 Master Synchronous Serial Ports MSSP1 Timers Timer0 Timer1 Timer2 Timer4 Timer6 2011 Microchip Technology Inc. PIC16(L)F1938/9 of the ● ● ● ● ● ● ● ● ● ● ● ● ● ● ...
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... LCD ECCP1 ECCP2 See applicable chapters for more information on peripherals. Note 1: DS41574A-page 16 Program Flash Memory CPU Figure 2-1 Timer1 Timer2 Timer4 Timer6 MSSP ECCP3 CCP4 CCP5 Preliminary EEPROM RAM PORTA PORTB PORTC PORTD PORTE Comparators EUSART 2011 Microchip Technology Inc. ...
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... Pin function is selectable via the APFCON register. Note 1: PIC16F1938/9 devices only. 2: PIC16(L)F1938 devices only. 3: PORTD is available on PIC16(L)F1939 devices only. 4: RE<2:0> are available on PIC16(L)F1939 devices only. 5: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Input Output Type Type TTL CMOS General purpose I/O. AN — ...
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... Comparator negative input. AN — Capacitive sensing input 3. ST CMOS Capture/Compare/PWM2. — CMOS PWM output. AN — LCD analog input. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Pin function is selectable via the APFCON register. Note 1: PIC16F1938/9 devices only. 2: PIC16(L)F1938 devices only. 3: PORTD is available on PIC16(L)F1939 devices only. 4: RE<2:0> are available on PIC16(L)F1939 devices only. 5: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Input Output Type Type TTL CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. AN — ...
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... LCD analog output. ST CMOS General purpose I/O. AN — Capacitive sensing input 13. — CMOS PWM output. — AN LCD analog output. = Schmitt Trigger input with CMOS levels I Preliminary Description OD = Open Drain 2 2 C™ = Schmitt Trigger input with I C levels 2011 Microchip Technology Inc. ...
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... Pin function is selectable via the APFCON register. Note 1: PIC16F1938/9 devices only. 2: PIC16(L)F1938 devices only. 3: PORTD is available on PIC16(L)F1939 devices only. 4: RE<2:0> are available on PIC16(L)F1939 devices only. 5: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Input Output Type Type ST CMOS General purpose I/O. AN — Capacitive sensing input 14. ...
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... PIC16(L)F1938/9 NOTES: DS41574A-page 22 Preliminary 2011 Microchip Technology Inc. ...
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... Section 3.5 “Indirect Addressing” 2.4 Instruction Set There are 49 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 29.0 “Instruction Set Summary” details. 2011 Microchip Technology Inc. PIC16(L)F1938/9 Saving”, for more for more Preliminary DS41574A-page 23 ...
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... Power-up Timer Oscillator Start-up Timer ALU ALU ALU Power- Reset Watchdog W reg Timer Brown-out Reset Preliminary RAM Addr 9 Indirect Addr 12 FSR0 Reg FSR reg FSR reg STATUS Reg STATUS reg STATUS reg MUX MUX MUX 2011 Microchip Technology Inc. ...
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... Section 11.0 “Data EEPROM and Flash Program Memory Control”. TABLE 3-1: DEVICE SIZES AND ADDRESSES Device / PIC16F1938 PIC16LF1938 / PIC16F1939 PIC16LF1939 2011 Microchip Technology Inc. PIC16(L)F1938/9 The following features are associated with access and control of program memory and data memory: • ...
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... BRW instruction is not available so the older table read 2000h method must be used. 3FFFh 4000h 7FFFh Preliminary Example 3-1. RETLW INSTRUCTION ;Add Index ;program counter to ;select data ;Index0 data ;Index1 data DATA_INDEX 2011 Microchip Technology Inc. ...
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... File Select Registers (FSR). See Section 3.5 for more information. Addressing” 2011 Microchip Technology Inc. PIC16(L)F1938/9 3.2.1 CORE REGISTERS The core registers contain the registers that directly affect the basic operation of the PIC16(L)F1938/9. These registers are listed below: • ...
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... Digit Borrow out bits, respectively, in subtraction. R-1/q R-1/q R/W-0 Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Value depends on condition (ADDWF, ADDLW, SUBLW, SUBWF instructions) Preliminary Section 29.0 Summary”). R/W-0/u R/W-0/u (1) ( bit 0 (1) (1) 2011 Microchip Technology Inc. ...
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... Microchip Technology Inc. PIC16(L)F1938/9 3.2.5 DEVICE MEMORY MAPS The memory maps for the device family are as shown in Table 3-2. TABLE 3-2: Device PIC16F1938 PIC16LF1938 PIC16F1939 PIC16LF1939 Section 3.5.2 Preliminary MEMORY MAP TABLES Banks Table No. 0-7 Table 3-3 8-15 Table ...
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TABLE 3-3: PIC16(L)F1938/9 MEMORY MAP, BANKS 0-7 BANK 0 BANK 1 000h INDF0 080h INDF0 100h 001h INDF1 081h INDF1 101h 002h PCL 082h PCL 102h 003h STATUS 083h STATUS 103h 004h FSR0L 084h FSR0L 104h 005h FSR0H 085h FSR0H ...
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TABLE 3-4: PIC16(L)F1938/9 MEMORY MAP, BANKS 8-15 BANK 8 BANK 9 INDF0 INDF0 400h 480h 500h INDF1 INDF1 401h 481h 501h PCL PCL 402h 482h 502h STATUS STATUS 403h 483h 503h FSR0L FSR0L 404h 484h 504h FSR0H FSR0H 405h 485h ...
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TABLE 3-5: PIC16(L)F1938/9 MEMORY MAP, BANKS 16-23 BANK 16 BANK 17 800h INDF0 880h INDF0 900h 801h INDF1 881h INDF1 901h 802h PCL 882h PCL 902h 803h STATUS 883h STATUS 903h 804h FSR0L 884h FSR0L 904h 805h FSR0H 885h FSR0H ...
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TABLE 3-6: PIC16(L)F1938/9 MEMORY MAP, BANKS 24-31 BANK 24 BANK 25 C00h INDF0 C80h INDF0 D00h C01h INDF1 C81h INDF1 D01h C02h PCL C82h PCL D02h C03h STATUS C83h STATUS D03h C04h FSR0L C84h FSR0L D04h C05h FSR0H C85h FSR0H ...
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... Unimplemented Read as ‘0’ 7EFh = Unimplemented data memory locations, read Legend: as ‘0’. Preliminary 2011 Microchip Technology Inc. ...
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... FECh FEDh STKPTR FEEh TOSL FEFh TOSH = Unimplemented data memory locations, read Legend: as ‘0’. 2011 Microchip Technology Inc. PIC16(L)F1938/9 3.2.6 SPECIAL FUNCTION REGISTERS SUMMARY The Special Function Register Summary for the device family are as follows: Device PIC16(L)F1938/9 Preliminary Bank(s) Page No ...
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... TMR1ON 0000 00-0 uuuu uu-u T1GSS<1:0> 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 T2CKPS<1:0> -000 0000 -000 0000 — — CPSOUT T0XCS 00-- 0000 00-- 0000 ---- 0000 ---- 0000 2011 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... ADFVR<1:0> 0q00 0000 0q00 0000 --- DACNSS 000- 00-0 000- 00-0 ---0 0000 ---0 0000 SRPS SRPR 0000 0000 0000 0000 SRRC2E SRRC1E 0000 0000 0000 0000 — — SSSEL CCP2SEL -000 0000 -000 0000 — — — — 2011 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... RSEN SEN 0000 0000 0000 0000 AHEN DHEN 0000 0000 0000 0000 — — — — — — — — — — — — — — — — 2011 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... PSS3BD<1:0> 0000 0000 0000 0000 STR3B STR3A ---0 0001 ---0 0001 — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 — — 2011 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... T4CKPS <1:0> -000 0000 -000 0000 — — — — — — — — 0000 0000 0000 0000 1111 1111 1111 1111 T6CKPS <1:0> -000 0000 -000 0000 — — 2011 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... COM0 COM0 SEG17 SEG16 xxxx xxxx uuuu uuuu COM0 COM0 SEG1 SEG0 xxxx xxxx uuuu uuuu COM1 COM1 SEG9 SEG8 xxxx xxxx uuuu uuuu COM1 COM1 SEG17 SEG16 xxxx xxxx uuuu uuuu COM1 COM1 2011 Microchip Technology Inc. ...
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... These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 SEG5 SEG4 SEG3 ...
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... INTF IOCIF 0000 0000 0000 0000 — — 2011 Microchip Technology Inc. ...
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... The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<14:8>, whose contents are transferred Note 1: to the upper byte of the program counter. These registers can be addressed from any bank. 2: These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. 3: Unimplemented, read as ‘1’. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 — — ...
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... If using BRW, load the W register with the desired unsigned address and execute BRW. The entire PC will 0 be loaded with the address BRW If using BRA, the entire PC will be loaded with the signed value of the operand of the BRA instruction. 0 BRA Preliminary 2011 Microchip Technology Inc. ...
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... RETFIE instructions or the vectoring to an interrupt address. FIGURE 3-4: ACCESSING THE STACK EXAMPLE 1 TOSH:TOSL TOSH:TOSL 2011 Microchip Technology Inc. PIC16(L)F1938/9 3.4.1 ACCESSING THE STACK The stack is available through the TOSH, TOSL and STKPTR registers. STKPTR is the current value of the Stack Pointer. TOSH:TOSL register pair points to the TOP of the stack ...
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... Program Counter and pop the stack. 0x09 0x08 0x07 STKPTR = 0x06 0x06 Return Address 0x05 Return Address 0x04 Return Address 0x03 Return Address 0x02 Return Address 0x01 Return Address 0x00 Return Address Preliminary 2011 Microchip Technology Inc. ...
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... The FSR registers form a 16-bit address that allows an addressing space with 65536 locations. These locations are divided into three memory regions: • Traditional Data Memory • Linear Data Memory • Program Flash Memory 2011 Microchip Technology Inc. PIC16(L)F1938/9 0x0F Return Address 0x0E Return Address ...
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... Not all memory regions are completely implemented. Consult device memory tables for memory limits. Note: DS41574A-page 54 0x0000 0x0000 Traditional Data Memory 0x0FFF 0x0FFF 0x1000 Reserved 0x1FFF 0x2000 Linear Data Memory 0x29AF 0x29B0 Reserved 0x7FFF 0x8000 0x0000 Program Flash Memory 0xFFFF 0x7FFF Preliminary 2011 Microchip Technology Inc. ...
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... FIGURE 3-9: TRADITIONAL DATA MEMORY MAP Direct Addressing From Opcode 4 BSR 6 0 Location Select Bank Select 0000 0x00 0x7F Bank 0 Bank 1 Bank 2 2011 Microchip Technology Inc. PIC16(L)F1938/9 Indirect Addressing 0 7 FSRxH Bank Select 0001 0010 1111 Bank 31 Preliminary ...
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... FIGURE 3-11: 7 FSRnH 0 1 Location Select 0x020 Bank 0 0x06F 0x0A0 Bank 1 0x0EF 0x120 Bank 2 0x16F 0xF20 Bank 30 0xF6F Preliminary the FSR/INDF interface. All PROGRAM FLASH MEMORY MAP FSRnL 0x8000 0x0000 Program Flash Memory (low 8 bits) 0x7FFF 0xFFFF 2011 Microchip Technology Inc. ...
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... Configuration Word 2 at 8008h. The DEBUG bit in Configuration Word 2 is Note: managed automatically development tools including debuggers and programmers. For normal device operation, this bit should be maintained as a ‘1’. 2011 Microchip Technology Inc. PIC16(L)F1938/9 by device Preliminary DS41574A-page 57 ...
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... Value when blank or after Bulk Erase (1) (2) (3) Pin Function Select bit PP pin function is MCLR; Weak pull-up enabled. PP pin function is digital input; MCLR internally disabled; Weak pull-up under control PP (1) Preliminary R/P-1/1 R/P-1/1 CPD CP bit 7 R/P-1/1 R/P-1/1 FOSC1 FOSC0 bit 0 2011 Microchip Technology Inc. ...
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... Enabling Brown-out Reset does not automatically enable Power-up Timer. Note 1: The entire data EEPROM will be erased when the code protection is turned off during an erase. 2: The entire program memory will be erased when the code protection is turned off. 3: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Preliminary DS41574A-page 59 ...
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... BORV STVREN R/P-1/1 U-1 U-1 (2) — — Unimplemented bit, read as ‘1’ Value when blank or after Bulk Erase (1) must be used for programming PP (3) (2) pin CAP Preliminary R/P-1/1 U-1 PLLEN — bit 7 R/P-1/1 R/P-1/1 WRT1 WRT0 bit 0 2011 Microchip Technology Inc. ...
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... See Section 4.5 “Device ID and Revision ID” information on accessing these memory locations. For more information on checksum calculation, see “PIC16F193X/LF193X/PIC16F194X/LF194X/PIC16LF 190X Memory Programming Specification” (DS41397). 2011 Microchip Technology Inc. PIC16(L)F1938/9 “Write such as for more ...
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... R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 13-5 DEV<8:0>: Device ID bits 100011101 = PIC16F1938 100011110 = PIC16F1939 100100101 = PIC16LF1938 100100110 = PIC16LF1939 bit 4-0 REV<4:0>: Revision ID bits These bits are used to identify the revision. This location cannot be written. Note 1: DS41574A-page 62 ...
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... XT, HS modes) and switch automatically to the internal oscillator. • Oscillator Start-up Timer (OST) ensures stability of crystal oscillator sources 2011 Microchip Technology Inc. PIC16(L)F1938/9 The oscillator module can be configured in one of eight clock modes. 1. ECL – External Clock Low-Power mode (0 MHz to 0 ...
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... WDT, PWRT, Fail-Safe Clock Monitor Two-Speed Start-up and other modules Preliminary Sleep CPU and T1OSC Peripherals Clock Control FOSC<2:0> SCS<1:0> Clock Source Option for other modules 2011 Microchip Technology Inc. ...
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... Configuration Word 1: • High power, 4-32 MHz (FOSC = 111) • Medium power, 0.5-4 MHz (FOSC = 110) • Low power, 0-0.5 MHz (FOSC = 101) 2011 Microchip Technology Inc. PIC16(L)F1938/9 The Oscillator Start-up Timer (OST) is disabled when EC mode is selected. Therefore, there is no delay in operation after a Power-on Reset (POR) or wake-up from Sleep ...
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... SPLLEN is ignored. Preliminary CERAMIC RESONATOR OPERATION ( MODE) ® PIC MCU OSC1/CLKIN To Internal Logic R (3) ( Sleep F OSC2/CLKOUT R S (1) ) may be required for S varies with the Oscillator mode F P Oscillator Start-up Timer (OST) Section 5.4 Mode”). 4X PLL 2011 Microchip Technology Inc. ) ...
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... MS1V-T1K 32.768 kHz Tuning Fork Crystal to a PIC16F690/SS” (DS91097) • AN1288, “Design Practices for Low-Power External Oscillators” (DS01288) 2011 Microchip Technology Inc. PIC16(L)F1938/9 5.2.1.6 The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required ...
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... OSCSTAT register indicates when the MFINTOSC is running and can be utilized. Preliminary (Register 5-3). Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. Internal Oscillator Figure 5-1). One of nine Section 5.2.2.7 “Internal for more information. 2011 Microchip Technology Inc. ...
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... Watchdog Timer (WDT) • Fail-Safe Clock Monitor (FSCM) The Low-Frequency Internal Oscillator Ready bit (LFIOFR) of the OSCSTAT register indicates when the LFINTOSC is running and can be utilized. 2011 Microchip Technology Inc. PIC16(L)F1938/9 5.2.2.5 Internal Oscillator Frequency Selection The system clock speed can be selected via software using the Internal Oscillator Frequency Select bits 5-3) ...
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... Clock switching time delays are shown in Start-up delay specifications are located in the oscillator tables in Specifications Chapter. Preliminary 2011 Microchip Technology Inc. Figure 5-7). If this is the Table 5-1. the applicable Electrical ...
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... IRCF <3:0> System Clock LFINTOSC HFINTOSC/MFINTOSC LFINTOSC Start-up Time HFINTOSC/ MFINTOSC IRCF <3:0> System Clock 2011 Microchip Technology Inc. PIC16(L)F1938/9 Start-up Time 2-cycle Sync 0 2-cycle Sync LFINTOSC turns off unless WDT or FSCM is enabled 2-cycle Sync ...
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... The Timer1 Oscillator Ready (T1OSCR) bit of the OSCSTAT register indicates whether the Timer1 oscillator is ready to be used. After the T1OSCR bit is set, the SCS bits can be configured to select the Timer1 oscillator. Start-up or Preliminary Section 21.0 for more 2011 Microchip Technology Inc. ...
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... Any clock source LFINTOSC Any clock source Timer1 Oscillator PLL inactive PLL active PLL inactive. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938/9 5.4.1 TWO-SPEED START-UP MODE CONFIGURATION Two-Speed Start-up mode is configured by the following settings: • IESO (of the Configuration Word Inter- nal/External Switchover bit (Two-Speed Start-up mode enabled). • ...
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... CHECKING TWO-SPEED CLOCK STATUS Checking the state of the OSTS bit of the OSCSTAT register will confirm if the microcontroller is running from the external clock source, as defined by the FOSC<2:0> bits in the Configuration Word 1, or the internal oscillator Preliminary 2011 Microchip Technology Inc. ...
Page 75
... The internal clock source chosen by the FSCM is determined by the IRCF<3:0> bits of the OSCCON register. This allows the internal oscillator to be configured before a failure occurs. 2011 Microchip Technology Inc. PIC16(L)F1938/9 5.5.3 FAIL-SAFE CONDITION CLEARING The Fail-Safe condition is cleared after a Reset, executing a SLEEP instruction or changing the SCS bits of the OSCCON register ...
Page 76
... Clock Monitor Output (Q) OSCFIF The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in Note: this example have been chosen for clarity. DS41574A-page 76 Oscillator Failure Test Test Preliminary Failure Detected Test 2011 Microchip Technology Inc. ...
Page 77
... SCS<1:0>: System Clock Select bits 1x = Internal oscillator block 01 = Timer1 oscillator 00 = Clock determined by FOSC<2:0> in Configuration Word 1. Duplicate frequency derived from HFINTOSC. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-1/1 R/W-1/1 IRCF<3:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Section 5 ...
Page 78
... HFINTOSC is at least 0.5% accurate 0 = HFINTOSC is not 0.5% accurate DS41574A-page 78 R-0/q R-0/q R-q/q HFIOFR HFIOFL MFIOFR U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets q = Conditional Preliminary R-0/0 R-0/q LFIOFR HFIOFS bit 0 2011 Microchip Technology Inc. ...
Page 79
... Shaded cells are not used by clock sources. Legend: PIC16F1938/9 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-0/0 R/W-0/0 R/W-0/0 TUN<5:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 80
... PIC16(L)F1938/9 NOTES: DS41574A-page 80 Preliminary 2011 Microchip Technology Inc. ...
Page 81
... SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Programming Mode Exit RESET Instruction Stack Overflow/Underflow Reset Stack Pointer External Reset MCLRE MCLR Sleep WDT Time-out Power-on Reset V DD Brown-out Reset BOR Enable 2011 Microchip Technology Inc. PIC16(L)F1938/9 PWRT Zero 64 ms LFINTOSC PWRTEN Preliminary Device Reset DS41574A-page 81 ...
Page 82
... V for a DD BOR , the device BORDC for more information. Device Device Operation upon Operation upon wake- up from release of POR Sleep (1) Waits for BOR ready Waits for BOR ready Begins immediately Begins immediately Begins immediately level. DD 2011 Microchip Technology Inc. ...
Page 83
... If BOREN <1:0> in Configuration Word BOR Enabled 0 = BOR Disabled bit 6-1 Unimplemented: Read as ‘0’ bit 0 BORRDY: Brown-out Reset Circuit Ready Status bit 1 = The Brown-out Reset circuit is active 0 = The Brown-out Reset circuit is inactive 2011 Microchip Technology Inc. PIC16(L)F1938/9 (1) T PWRT < T PWRT PWRT (1) T ...
Page 84
... Upon bringing MCLR high, the device will begin execution immediately (see is useful for testing purposes or to synchronize more than one device operating in parallel. Section 10.0 Table 6-4 for Preliminary Timer configuration. See for more information. Figure 6-3). This 2011 Microchip Technology Inc. ...
Page 85
... FIGURE 6-3: RESET START-UP SEQUENCE V DD Internal POR Power-Up Timer MCLR Internal RESET Oscillator Modes External Crystal Oscillator Start-Up Timer Oscillator F OSC Internal Oscillator Oscillator F OSC External Clock (EC) CLKIN F OSC 2011 Microchip Technology Inc. PIC16(L)F1938/9 T PWRT T MCLR T OST Preliminary DS41574A-page 85 ...
Page 86
... Program Counter 0000h ---1 1000 0000h ---u uuuu 0000h ---1 0uuu 0000h ---0 uuuu ---0 0uuu 0000h ---1 1uuu ( ---1 0uuu 0000h ---u uuuu 0000h ---u uuuu 0000h ---u uuuu Preliminary Condition STATUS PCON Register Register 00-- 110x uu-- 0uuu uu-- 0uuu uu-- uuuu uu-- uuuu 00-- 11u0 uu-- uuuu uu-- u0uu 1u-- uuuu u1-- uuuu 2011 Microchip Technology Inc. ...
Page 87
... A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0 BOR: Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Power-on Reset or Brown-out Reset occurs) 2011 Microchip Technology Inc. PIC16(L)F1938/9 6-2. U-0 R/W/HC-1/q R/W/HC-1/q — ...
Page 88
... Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation. Note 1: DS41574A-page 88 Bit 5 Bit 4 Bit 3 Bit 2 — — — — — — RMCLR RI — WDTPS<4:0> Preliminary Register Bit 1 Bit 0 on Page — BORRDY 83 POR BOR SWDTEN 109 2011 Microchip Technology Inc. ...
Page 89
... A block diagram of the interrupt logic is shown in Figure 7-1. FIGURE 7-1: INTERRUPT LOGIC IOCBNx RBx IOCBPx Q4Q1 Q4Q1 2011 Microchip Technology Inc. PIC16(L)F1938/9 Q4Q1 Edge Detect Data Bus = Write IOCBFx CK From all other IOCBFx Individual Pin Detectors Q4Q1 Preliminary To Data Bus IOCBFx IOCIE ...
Page 90
... The latency for synchronous interrupts instruction cycles. For asynchronous interrupts, the latency instruction cycles, depending on when the interrupt occurs. See and Figure 7-3 for more details. Preliminary 2011 Microchip Technology Inc. Figure 7-2 ...
Page 91
... PC PC Execute 2 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC Interrupt GIE PC Execute 3 Cycle Instruction at PC 2011 Microchip Technology Inc. PIC16(L)F1938/9 Interrupt Sampled during Q1 PC+1 0004h Inst(PC) NOP NOP PC+1/FSR New PC/ 0004h ADDR PC+1 Inst(PC) NOP NOP FSR ADDR ...
Page 92
... INTF is enabled to be set any time during the Q4-Q1 cycles. DS41574A-page (1) (2) Interrupt Latency Inst ( — Dummy Cycle Dummy Cycle Inst (PC) . Synchronous latency = 3 Preliminary 0004h 0005h Inst (0004h) Inst (0005h) Inst (0004h) , where T = instruction cycle time 2011 Microchip Technology Inc. ...
Page 93
... Shadow register should be modified and the value will be restored when exiting the ISR. The Shadow registers are available in Bank 31 and are readable and writable. Depending on the user’s appli- cation, other registers may also need to be saved. 2011 Microchip Technology Inc. PIC16(L)F1938/9 Preliminary DS41574A-page 93 ...
Page 94
... User software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. R/W-0/0 R/W-0/0 R/W-0/0 INTE IOCIE TMR0IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R-0/0 INTF IOCIF bit 0 2011 Microchip Technology Inc. ...
Page 95
... Disables the Timer2 to PR2 match interrupt bit 0 TMR1IE: Timer1 Overflow Interrupt Enable bit 1 = Enables the Timer1 overflow interrupt 0 = Disables the Timer1 overflow interrupt 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
Page 96
... Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. R/W-0/0 R/W-0/0 R/W-0/0 EEIE BCLIE LCDIE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary U-0 R/W-0/0 — CCP2IE bit 0 2011 Microchip Technology Inc. ...
Page 97
... TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enables the TMR4 to PR4 Match interrupt 0 = Disables the TMR4 to PR4 Match interrupt bit 0 Unimplemented: Read as ‘0’ 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit PEIE of the INTCON register must be Note: set to enable any peripheral interrupt. ...
Page 98
... R-0/0 R/W-0/0 R/W-0/0 TXIF SSPIF CCP1IF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary 2011 Microchip Technology Inc. should ensure the R/W-0/0 R/W-0/0 TMR2IF TMR1IF bit 0 ...
Page 99
... Unimplemented: Read as ‘0’ bit 0 CCP2IF: CCP2 Interrupt Flag bit 1 = Interrupt is pending 0 = Interrupt is not pending 2011 Microchip Technology Inc. PIC16(L)F1938/9 Interrupt flag bits are set when an interrupt Note: condition occurs, regardless of the state of its corresponding enable bit or the Global Enable bit, GIE, of the INTCON register ...
Page 100
... R/W-0/0 R/W-0/0 R/W-0/0 CCP3IF TMR6IF — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary should ensure the R/W-0/0 R/W-0/0 TMR4IF — bit 0 2011 Microchip Technology Inc. ...
Page 101
... CCP5IE PIR1 TMR1GIF ADIF PIR2 OSFIF C2IF PIR3 — CCP5IF Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupts. 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INTE IOCIE TMR0IF PSA RCIE TXIE ...
Page 102
... PIC16(L)F1938/9 NOTES: DS41574A-page 102 Preliminary 2011 Microchip Technology Inc. ...
Page 103
... Shaded cells are not used by LDO. Legend: PIC16F1938/9 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938/9 On power-up, the external capacitor will load the LDO voltage regulator. To prevent erroneous operation, the device is held in Reset while a constant current source charges the external capacitor ...
Page 104
... PIC16(L)F1938/9 NOTES: DS41574A-page 104 Preliminary 2011 Microchip Technology Inc. ...
Page 105
... Section 17.0 “Digital-to-Analog Con- and Section 14.0 “Fixed Volt- verter (DAC) Module” age Reference (FVR)” for more information on these modules. 2011 Microchip Technology Inc. PIC16(L)F1938/9 9.1 Wake-up from Sleep The device can wake-up from Sleep through one of the following events: 1 ...
Page 106
... Inst(0004h) Inst(0005h) Dummy Cycle Inst(0004h) Register on Bit 1 Bit 0 Page INTF IOCIF 94 IOCBF1 IOCBF0 148 IOCBN1 IOCBN0 148 IOCBP1 IOCBP0 148 TMR2IE TMR1IE 95 — CCP2IE 96 TMR4IE — 97 TMR2IF TMR1IF 98 — CCP2IF 99 TMR4IF — 100 SWDTEN 109 2011 Microchip Technology Inc. ...
Page 107
... Configurable time-out period is from 256 seconds (typical) • Multiple Reset conditions • Operation during Sleep FIGURE 10-1: WATCHDOG TIMER BLOCK DIAGRAM WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep 2011 Microchip Technology Inc. PIC16(L)F1938/9 23-bit Programmable LFINTOSC Prescaler WDT WDTPS<4:0> Preliminary WDT Time-out DS41574A-page 107 ...
Page 108
... STATUS register are changed to indicate the event. See WDT Mode Section 3.0 “Memory Organization” register (Register 3-1) for more information. Active Active Disabled Active Disabled Disabled Preliminary Section 5.0 “Oscillator for more and STATUS WDT Cleared Cleared until the end of OST Unaffected 2011 Microchip Technology Inc. ...
Page 109
... SWDTEN: Software Enable/Disable for Watchdog Timer bit If WDTE<1:0> = 00: This bit is ignored. If WDTE<1:0> WDT is turned WDT is turned off If WDTE<1:0> = 1x: This bit is ignored. 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-1/1 R/W-0/0 R/W-1/1 WDTPS<4:0> Unimplemented bit, read as ‘0’ -m/n = Value at POR and BOR/Value at all other Resets ...
Page 110
... Bit 2 IRCF<3:0> — — WDTPS<4:0> Bit 13/5 Bit 12/4 Bit 11/3 Bit 10/2 FCMEN IESO CLKOUTEN PWRTE WDTE<1:0> Preliminary Register Bit 1 Bit 0 on Page SCS<1:0> SWDTEN 109 Register Bit 9/1 Bit 8/0 on Page BOREN<1:0> CPD 58 FOSC<2:0> 2011 Microchip Technology Inc. ...
Page 111
... When code-protected, the CPU may continue to read and write the data EEPROM memory and Flash program memory. 2011 Microchip Technology Inc. PIC16(L)F1938/9 11.1 EEADRL and EEADRH Registers The EEADRH:EEADRL register pair can address maximum of 256 bytes of data EEPROM maximum of 32K words of program memory ...
Page 112
... CPU is able to read and write data to the data EEPROM recommended to code-protect the pro- gram memory when code-protecting data memory. This prevents anyone from replacing your program with a program that will access the contents of the data EEPROM. Preliminary 2011 Microchip Technology Inc. (Register 5-1) ...
Page 113
... FLASH PROGRAM MEMORY READ CYCLE EXECUTION Flash ADDR Flash Data INSTR (PC) BSF EECON1,RD INSTR( executed here executed here RD bit EEDATH EEDATL Register EERHLT 2011 Microchip Technology Inc. PIC16(L)F1938/9 EEADRH,EEADRL PC+3 INSTR ( EEDATH,EEDATL INSTR ( INSTR( Forced NOP executed here executed here Preliminary INSTR ( ...
Page 114
... NOPs. This prevents the user from executing a two-cycle instruction after the RD bit is set. 2: Flash program memory can be read regardless of the setting of the CP bit. Latches/ Boundary 8 words, 000 Preliminary instruction on the next 2011 Microchip Technology Inc. ...
Page 115
... NOP ; Executed NOP ; Ignored BSF INTCON,GIE ; Restore interrupts MOVF EEDATL,W ; Get LSB of word MOVWF PROG_DATA_LO ; Store in user location MOVF EEDATH,W ; Get MSB of word MOVWF PROG_DATA_HI ; Store in user location 2011 Microchip Technology Inc. PIC16(L)F1938/9 (Figure 11-1) (Figure 11-1) Preliminary DS41574A-page 115 ...
Page 116
... EEADRH:EEADRL register pair; the eight words of data are loaded using indirect addressing. The code Note: Example 11-5 times to fully program an erased program memory row. Preliminary 2011 Microchip Technology Inc. 11-5. The initial address is sequence provided in must be repeated multiple ...
Page 117
... EEADRL<2:0> = 000 EEADRL<2:0> = 001 Buffer Register 2011 Microchip Technology Inc. PIC16(L)F1938/9 continue to run. The processor does not stall when LWLO = 1, loading the write latches. After the write cycle, the processor will resume operation with the third instruction after the EECON1 WRITE instruction. ...
Page 118
... Write AAh ; Set WR bit to begin erase ; Any instructions here are ignored as processor ; halts to begin erase sequence ; Processor will stop here and wait for erase complete. ; after erase processor continues with 3rd instruction ; Disable writes ; Enable interrupts Preliminary 2011 Microchip Technology Inc. ...
Page 119
... EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1,WR NOP NOP BCF EECON1,WREN BSF INTCON,GIE 2011 Microchip Technology Inc. PIC16(L)F1938/9 ; Disable ints so required sequences will execute properly ; Bank 3 ; Load initial address ; ; ; ; Load initial data address ; ; ; Point to program memory ; Not configuration space ; Enable writes ...
Page 120
... Table When read access is initiated on an address outside the parameters listed in register pair is cleared. Function Read Access User IDs Yes Yes Yes Figure 11-1) Figure 11-1) Preliminary 11-2. Table 11-2, the EEDATH:EEDATL Write Access Yes No No 2011 Microchip Technology Inc. ...
Page 121
... EEPROM WRITE VERIFY BANKSEL EEDATL ; MOVF EEDATL, W ;EEDATL not changed ;from previous write BSF EECON1, RD ;YES, Read the ;value written XORWF EEDATL BTFSS STATUS, Z ;Is data the same GOTO WRITE_ERR ;No, handle error : ;Yes, continue 2011 Microchip Technology Inc. PIC16(L)F1938/9 Preliminary DS41574A-page 121 ...
Page 122
... Value at POR and BOR/Value at all other Resets R/W-0/0 R/W-0/0 R/W-0/0 EEADR<14:8> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u bit 0 R/W-x/u R/W-x/u bit 0 R/W-0/0 R/W-0/0 bit 0 R/W-0/0 R/W-0/0 bit 0 2011 Microchip Technology Inc. ...
Page 123
... RD: Read Control bit 1 = Initiates a program Flash or data EEPROM read. Read takes one cycle cleared in hardware. The RD bit can only be set (not cleared) in software Does not initiate a program Flash or data EEPROM data read. 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W/HC-0/0 R/W-x/q R/W-0/0 ...
Page 124
... EEADRL<7:0> EEADRH<6:0 EEDATL<7:0> EEDATH<5:0> INTE IOCIE TMR0IF EEIE BCLIE LCDIE C1IF EEIF BCLIF LCDIF Preliminary W-0/0 W-0/0 W-0/0 bit 0 Register on Bit 1 Bit 0 Page WR RD 123 111* 122 122 122 122 INTF IOCIF 94 — CCP2IE 96 — CCP2IF 99 2011 Microchip Technology Inc. ...
Page 125
... Disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. A simplified model of a generic I/O port, without the interfaces to other peripherals, is shown in 2011 Microchip Technology Inc. PIC16(L)F1938/9 FIGURE 12-1: D Write LATx ...
Page 126
... Timer1 Gate • SR Latch SRNQ output • Comparator C2 output These bits have no effect on the values of any TRIS register. PORT and TRIS overrides will be routed to the correct pin. The unselected pin will be unaffected. DS41574A-page 126 Preliminary 2011 Microchip Technology Inc. ...
Page 127
... SSSEL: SS Input Pin Selection bit function is on RA5/AN4/C2OUT/SRNQ/SS/CPS7/SEG5 function is on RA0/AN0/C12IN0-/C2OUT/SRNQ/SS/SEG12/V bit 0 CCP2SEL: CCP2 Input/Output Pin Selection bit 0 = CCP2/P2A function is on RC1/T1OSI/CCP2/P2A 1 = CCP2/P2A function is on RB3/AN9/C12IN2-/CPS3/CCP2/P2A/VLCD3 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-0/0 R/W-0/0 R/W-0/0 P2BSEL SRNQSEL C2OUTSEL U = Unimplemented bit, read as ‘ ...
Page 128
... CLKOUT (enabled by Config. Word) SEG1 (LCD) RA6 RA7 OSC1/CLKIN (enabled by Config. Word) SEG2 (LCD) RA7 Priority listed from highest to lowest. Note 1: Preliminary 12-2. Table 12-2. PORTA OUTPUT PRIORITY (1) Function Priority CAP (enabled by Config. Word) CAP (enabled by Config. Word) CAP 2011 Microchip Technology Inc. ...
Page 129
... Bit is cleared bit 7-0 LATA<7:0>: PORTA Output Latch Value bits Writes to PORTA are actually written to corresponding LATA register. Reads from PORTA register is return Note 1: of actual I/O pin values. 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-x/u R/W-x/u R/W-x/u RA4 ...
Page 130
... DS41574A-page 130 R/W-1/1 R/W-1/1 R/W-1/1 ANSA4 ANSA3 ANSA2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) . Digital input buffer disabled. Preliminary R/W-1/1 R/W-1/1 ANSA1 ANSA0 bit 0 2011 Microchip Technology Inc. ...
Page 131
... MCLRE 13:8 — — CONFIG2 7:0 — — — = unimplemented location, read as ‘0’. Shaded cells are not used by PORTA. Legend: PIC16F1938/9 only. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ADCS<2:0> — ADNREF ANSA5 ANSA4 ANSA3 ...
Page 132
... The ANSELB bits default to the Analog Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. Section 13.0 Preliminary (Register 12-9) is used to 2011 Microchip Technology Inc. ...
Page 133
... COM1 P2B, 28-pin only CCP3/P3A RB5 RB6 ICSPCLK (Programming) ICDCLK (enabled by Config. Word) SEG14 (LCD) RB6 RB7 ICSPDAT (Programming) ICDDAT (enabled by Config. Word) SEG13 (LCD) RB7 Priority listed from highest to lowest. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938/9 (1) Preliminary DS41574A-page 133 ...
Page 134
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATB4 LATB3 LATB2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RB1 RB0 bit 0 R/W-1/1 R/W-1/1 TRISB1 TRISB0 bit 0 R/W-x/u R/W-x/u LATB1 LATB0 bit 0 2011 Microchip Technology Inc. ...
Page 135
... Pull-up enabled 0 = Pull-up disabled Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled. Note 1: The weak pull-up device is automatically disabled if the pin is in configured as an output. 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-1/1 R/W-1/1 R/W-1/1 ANSB4 ANSB3 ANSB2 U = Unimplemented bit, read as ‘ ...
Page 136
... IOCBN1 IOCBN0 148 IOCBF1 IOCBF0 148 LATB2 LATB1 LATB0 134 LMUX<1:0> 329 SE2 SE1 SE0 333 SE10 SE9 SE8 333 PS<2:0> 189 RB2 RB1 RB0 134 T1GSS<1:0> 200 TRISB2 TRISB1 TRISB0 134 WPUB2 WPUB1 WPUB0 135 2011 Microchip Technology Inc. ...
Page 137
... The user should ensure the bits in the TRISC register are maintained set when using them as analog inputs. I/O pins configured as analog input always read ‘0’. 2011 Microchip Technology Inc. PIC16(L)F1938/9 12.4.1 PORTC FUNCTIONS AND OUTPUT PRIORITIES Each PORTC pin is multiplexed with other functions ...
Page 138
... Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u LATC4 LATC3 LATC2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u RC1 RC0 bit 0 R/W-1/1 R/W-1/1 TRISC1 TRISC0 bit 0 R/W-x/u R/W-x/u LATC1 LATC0 bit 0 2011 Microchip Technology Inc. ...
Page 139
... SMP CKE T1CON TMR1CS<1:0> TXSTA CSRC TX9 TRISC TRISC7 TRISC6 x = unknown unchanged unimplemented locations read as ‘0’. Shaded cells are not used by PORTC. Legend: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 T1GSEL P2BSEL SRNQSEL C2OUTSEL DCxB<1:0> CCPxM<3:0> LATC5 ...
Page 140
... Function Priority COM3 (LCD) RD0 CCP4 (CCP) RD1 P2B (CCP) RD2 SEG16 (LCD) P2C (CCP) RD3 SEG17 (LCD) P2D (CCP) RD4 SEG18 (LCD) P1B (CCP) RD5 SEG19 (LCD) P1C (CCP) RD6 SEG20 (LCD) P1D (CCP) RD7 2011 Microchip Technology Inc. ...
Page 141
... LATD<7:0>: PORTD Output Latch Value bits Writes to PORTD are actually written to corresponding LATD register. Reads from PORTD register is Note 1: return of actual I/O pin values. PORTD implemented on PIC16(L)F1939 devices only. 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 (1) R/W-x/u R/W-x/u R/W-x/u RD4 ...
Page 142
... TRISD4 TRISD3 TRISD2 Preliminary (2) R/W-1/1 R/W-1/1 ANSD1 ANSD0 bit 0 (1) Register on Bit 1 Bit 0 Page ANSD1 ANSD0 142 230 CPSOUT T0XCS 323 324 LATD1 LATD0 141 LMUX<1:0> 329 SE17 SE16 333 RD1 RD0 141 TRISD1 TRISD0 141 2011 Microchip Technology Inc. ...
Page 143
... Note: mode after Reset. To use any pins as digital general purpose or peripheral inputs, the corresponding ANSEL bits must be initialized to ‘0’ by user software. 2011 Microchip Technology Inc. PIC16(L)F1938/9 12.6.2 PORTE FUNCTIONS AND OUTPUT PRIORITIES Each PORTE pin is multiplexed with other functions. The ...
Page 144
... Value at POR and BOR/Value at all other Resets (1) (2) U-0 U-1 R/W-1 (1) TRISE2 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets (1) Preliminary R/W-x/u R/W-x/u (1) (1) RE1 RE0 bit 0 R/W-1 R/W-1 (1) (1) TRISE1 TRISE0 bit 0 2011 Microchip Technology Inc. ...
Page 145
... When setting a pin to an analog input, the corresponding TRIS bit must be set to Input mode in order to Note 1: allow external control of the voltage on the pin. ANSELE register is not implemented on the PIC16(L)F1938. Read as ‘0’ 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 U-0 U-0 R/W-x/u ...
Page 146
... Register Bit 1 Bit 0 on Page 159 GO/DONE ADON (1) (1) (1) ANSE1 ANSE0 145 230 (1) (1) (1) LATE1 LATE0 145 LMUX<1:0> 329 SE17 SE16 333 (1) (1) (1) RE1 RE0 144 (1) (1) (1) TRISE1 TRISE0 144 — — 146 2011 Microchip Technology Inc. ...
Page 147
... R RBx IOCBPx 2011 Microchip Technology Inc. PIC16(L)F1938/9 13.3 Interrupt Flags The IOCBFx bits located in the IOCBF register are status flags that correspond to the interrupt-on-change pins of PORTB expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the IOCIE bit is set ...
Page 148
... R/W/HS-0/0 IOCBF4 IOCBF3 IOCBF2 U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HS - Bit is set in hardware Preliminary R/W-0/0 R/W-0/0 IOCBP1 IOCBP0 bit 0 R/W-0/0 R/W-0/0 IOCBN1 IOCBN0 bit 0 R/W/HS-0/0 R/W/HS-0/0 IOCBF1 IOCBF0 bit 0 2011 Microchip Technology Inc. ...
Page 149
... IOCBF7 IOCBF6 IOCBN IOCBN7 IOCBN6 IOCBP IOCBP7 IOCBP6 TRISB7 TRISB6 TRISB Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used by interrupt-on-change. 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 ANSB5 ANSB4 ANSB3 ANSB2 TMR0IE INTE IOCIE ...
Page 150
... PIC16(L)F1938/9 NOTES: DS41574A-page 150 Preliminary 2011 Microchip Technology Inc. ...
Page 151
... Each FIGURE 14-1: VOLTAGE REFERENCE BLOCK DIAGRAM ADFVR<1:0> CDAFVR<1:0> FVREN FVRRDY 2011 Microchip Technology Inc. PIC16(L)F1938/9 amplifier can be configured to amplify the reference voltage by 1x 4x, to produce the three possible voltage levels. The ADFVR<1:0> bits of the FVRCON register are , with 1.024V, used to enable and configure the gain amplifier settings for the reference supplied to the ADC module ...
Page 152
... Value at POR and BOR/Value at all other Resets q = Value depends on condition (1) (3) (3) (Low Range) (High Range Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> Preliminary R/W-0/0 R/W-0/0 ADFVR<1:0> bit 0 (2) (2) (2) (2) Register Bit 1 Bit 0 on page ADFVR<1:0> 152 2011 Microchip Technology Inc. ...
Page 153
... Temperature Sensor DAC FVR Buffer1 CHS<4:0> Note 1: When ADON = 0, all multiplexer inputs are disconnected. 2: Not available on PIC16(L)F1938. 2011 Microchip Technology Inc. PIC16(L)F1938/9 The ADC can generate an interrupt upon completion of a conversion. This interrupt can be used to wake-up the device from Sleep. (ADC) ...
Page 154
... ADC clock selections. Unless using the F Note: system clock frequency will change the ADC adversely affect the ADC result. Section 15.2 Preliminary AD Figure 15-2. specifica- AD Table 15-1 gives exam- , any changes in the RC clock frequency, which may 2011 Microchip Technology Inc. ...
Page 155
... Sleep mode. FIGURE 15-2: ANALOG-TO-DIGITAL CONVERSION Conversion starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit 2011 Microchip Technology Inc. PIC16(L)F1938 DEVICE OPERATING FREQUENCIES AD S Device Frequency (F Device Frequency (F 20 MHz 16 MHz (2) (2) (2) 100 ns 125 ns (2) (2) (2) 200 ns ...
Page 156
... ADCON1 register controls the output format. Figure 15-3 shows the two output formats. ADRESH LSB bit 0 bit 7 10-bit A/D Result MSB bit 0 bit 7 10-bit A/D Result Preliminary ADRESL bit 0 Unimplemented: Read as ‘0’ LSB bit 0 2011 Microchip Technology Inc. ...
Page 157
... A device Reset forces all registers to their Note: Reset state. Thus, the ADC module is turned off and any pending conversion is terminated. 2011 Microchip Technology Inc. PIC16(L)F1938/9 15.2.4 ADC OPERATION DURING SLEEP The ADC module can operate during Sleep. This requires the ADC clock source to be set to the F option ...
Page 158
... MOVF ADRESL,W MOVWF RESULTLO Preliminary A/D CONVERSION ; ;clock ;Vdd and Vss Vref ; ;Set RA0 to input ; ;Set RA0 to analog ; ;Turn ADC On ;Acquisiton delay ;No, test again ; ;Read upper 2 bits ;store in GPR space ; ;Read lower 8 bits ;Store in GPR space 2011 Microchip Technology Inc. ...
Page 159
... See Section 14.0 “Fixed Voltage Reference (FVR)” for more information. 2: See 3: Section 16.0 “Temperature Indicator Module” Not available on the PIC16(L)F1938. 4: 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-0/0 R/W-0/0 R/W-0/0 CHS<4:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 160
... ADNREF U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets SS (1) - pin REF DD (1) + pin REF + pin as the source of the positive reference, be aware that a REF Preliminary R/W-0/0 R/W-0/0 ADPREF<1:0> bit 0 (1) 2011 Microchip Technology Inc. ...
Page 161
... Bit is set ‘0’ = Bit is cleared bit 7-6 ADRES<1:0>: ADC Result Register bits Lower 2 bits of 10-bit conversion result bit 5-0 Reserved: Do not use. 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-x/u R/W-x/u R/W-x/u ADRES<9:2> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 162
... U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets R/W-x/u R/W-x/u R/W-x/u ADRES<7:0> Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-x/u R/W-x/u ADRES<9:8> bit 0 R/W-x/u R/W-x/u bit 0 2011 Microchip Technology Inc. ...
Page 163
... REF 2: The charge holding capacitor (C 3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin leakage specification. 2011 Microchip Technology Inc. PIC16(L)F1938/9 source impedance is decreased, the acquisition time may be decreased. After the analog input channel is selected (or changed), an A/D acquisition must be done before the conversion can be started ...
Page 164
... V - REF DS41574A-page 164 V DD Sampling Switch 0. Rss R IC LEAKAGE (1) I 0. Full-Scale Range 0.5 LSB Zero-Scale Full-Scale Transition V REF Transition Preliminary HOLD REF Sampling Switch (k) Analog Input Voltage 1.5 LSB + 2011 Microchip Technology Inc. ...
Page 165
... Shaded cells are not Legend: used for ADC module. These registers/bits are not implemented on PIC16(L)F1938 devices, read as ‘0’. Note 1: Unimplemented, read as ‘1’. 2: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 CHS<4:0> ...
Page 166
... PIC16(L)F1938/9 NOTES: DS41574A-page 166 Preliminary 2011 Microchip Technology Inc. ...
Page 167
... The low range is selected by clearing the TSRNG bit of the FVRCON register. The low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. The low range is provided for low voltage operation. 2011 Microchip Technology Inc. PIC16(L)F1938/9 FIGURE 16-1: 16.2 Minimum Operating V ...
Page 168
... PIC16(L)F1938/9 NOTES: DS41574A-page 168 Preliminary 2011 Microchip Technology Inc. ...
Page 169
... DAC output value. The value of the individual resistors within the ladder can be found in the applicable Electrical Specifications chapter. 2011 Microchip Technology Inc. PIC16(L)F1938/9 17.1 Output Voltage Selection The DAC has 32 voltage level ranges. The 32 levels are set with the DACR< ...
Page 170
... VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE ® PIC MCU DAC R Module Voltage Reference Output Impedance DS41574A-page 170 Digital-to-Analog Converter (DAC) V SOURCE + Steps SOURCE - + DACOUT – Preliminary DACR<4:0> 5 DAC (To Comparator, CPS and ADC Modules) DACOUT DACOE Buffered DAC Output 2011 Microchip Technology Inc. ...
Page 171
... DAC is disabled. • DAC output voltage is removed from the DACOUT pin. • The DACR<4:0> range select bits are cleared. 2011 Microchip Technology Inc. PIC16(L)F1938/9 This is also the method used to output the voltage level from the FVR to an output pin. See “ ...
Page 172
... Value at POR and BOR/Value at all other Resets Bit 5 Bit 4 Bit 3 Bit 2 TSEN TSRNG CDAFVR<1:0> DACOE — DACPSS<1:0> — DACR<4:0> Preliminary U-0 R/W-0/0 — DACNSS bit 0 R/W-0/0 R/W-0/0 bit 0 Register Bit 1 Bit 0 on page ADFVR<1:0> 140 — DACNSS 172 172 2011 Microchip Technology Inc. ...
Page 173
... When the analog voltage at V less than the analog voltage the output of the IN comparator is a digital low level. When the analog voltage greater than the analog voltage the output of the comparator is a digital high level. IN 2011 Microchip Technology Inc. PIC16(L)F1938/9 FIGURE 18- ...
Page 174
... Output of comparator can be frozen during debugging. 3: DS41574A-page 174 (1) Interrupt Interrupt C POL ( CxHYS D (from Timer1) T1CLK Preliminary CxINTP det Set CxIF CxINTN det C OUT X To Data Bus Q MC OUT X To ECCP PWM Logic C SYNC TRIS bit C OUT Timer1 or SR Latch SYNCC OUT X 2011 Microchip Technology Inc. ...
Page 175
... The internal output of the comparator is latched with each instruction cycle. Unless otherwise specified, external outputs are not latched. 2011 Microchip Technology Inc. PIC16(L)F1938/9 18.2.3 COMPARATOR OUTPUT POLARITY Inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. The ...
Page 176
... See Section 14.0 “Fixed Voltage Reference (FVR)” for more information on the Fixed Voltage Reference module. See Section 17.0 “Digital-to-Analog for more information on the DAC input (DAC) Module” signal. Any time the comparator is disabled (CxON = 0), all comparator inputs are disabled. Preliminary 2011 Microchip Technology Inc. Converter ...
Page 177
... ECCP Auto-Shutdown mode. 2011 Microchip Technology Inc. PIC16(L)F1938/9 18.10 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-3 ...
Page 178
... Input Capacitance PIN I = Leakage Current at the pin due to various junctions LEAKAGE R = Interconnect Resistance Source Impedance Analog Voltage Threshold Voltage T Note 1: See the applicable Electrical Specifications Chapter DS41574A-page 178 V DD 0. (1) LEAKAGE 0. Vss Preliminary To Comparator 2011 Microchip Technology Inc. ...
Page 179
... CxSYNC: Comparator Output Synchronous Mode bit 1 = Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source Comparator output to Timer1 and I/O pin is asynchronous. 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-0/0 U-0 R/W-1/1 ...
Page 180
... Value at POR and BOR/Value at all other Resets SS U-0 U-0 U-0 — — Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets Preliminary R/W-0/0 R/W-0/0 CxNCH<1:0> — bit 0 R-0/0 R-0/0 MC2OUT MC1OUT — bit 0 2011 Microchip Technology Inc. ...
Page 181
... TRISA7 TRISA6 TRISB TRISB7 TRISB6 ANSELA — — ANSELB — — — = unimplemented location, read as ‘0’. Shaded cells are unused by the comparator module. Legend: 2011 Microchip Technology Inc. PIC16(L)F1938/9 Bit 5 Bit 4 Bit 3 Bit 2 C1OE C1POL --- C1SP C2OE C2POL — ...
Page 182
... PIC16(L)F1938/9 NOTES: DS41574A-page 182 Preliminary 2011 Microchip Technology Inc. ...
Page 183
... Enabling both the Set and Reset inputs Note: from any one source at the same time may result in indeterminate operation, as the Reset dominance cannot be assured. 2011 Microchip Technology Inc. PIC16(L)F1938/9 19.2 Latch Output The SRQEN and SRNQEN bits of the SRCON0 regis- ter control the Q and Q latch outputs ...
Page 184
... SRRPE SRCLK SRRCKE (3) SYNCC2OUT SRRC2E (3) SYNCC1OUT SRRC1E and simultaneously Note 1: Pulse generator causes a 1 Q-state pulse width. 2: Name denotes the connection point at the comparator output. 3: DS41574A-page 184 SRLEN SRQEN (1) Latch R Q SRLEN SRNQEN Preliminary 2011 Microchip Technology Inc. SRQ SRNQ ...
Page 185
... Pulse set input for 1 Q-clock period effect on set input. bit 0 SRPR: Pulse Reset Input of the SR Latch bit 1 = Pulse Reset input for 1 Q-clock period effect on Reset input. Set only, always reads back ‘ 0 ’. Note 1: 2011 Microchip Technology Inc. PIC16(L)F1938 MHz MHz OSC OSC 39 ...
Page 186
... ANSA4 ANSA3 ANSA2 SRQEN SRNQEN SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E TRISA5 TRISA4 TRISA3 TRISA2 Preliminary R/W-0/0 R/W-0/0 SRRC2E SRRC1E bit 0 Register Bit 1 Bit 0 on Page ANSA1 ANSA0 130 SRPS SRPR 185 186 TRISA1 TRISA0 129 2011 Microchip Technology Inc. ...
Page 187
... From CPSCLK 1 TMR0CS TMR0SE T0XCS 2011 Microchip Technology Inc. PIC16(L)F1938/9 When TMR0 is written, the increment is inhibited for two instruction cycles immediately following the write. The value written to the TMR0 register Note: can be adjusted, in order to account for the two instruction cycle delay when TMR0 is written ...
Page 188
... Electrical Specifications Chapter. 20.1.6 OPERATION DURING SLEEP Timer0 cannot operate while the processor is in Sleep mode. The contents of the TMR0 register will remain unchanged while the processor is in Sleep mode. DS41574A-page 188 Preliminary 2011 Microchip Technology Inc. ...
Page 189
... Timer0 Module Register TRISA TRISA7 TRISA6 Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module. * Page provides register information. 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-1/1 R/W-1/1 R/W-1/1 TMR0SE PSA U = Unimplemented bit, read as ‘0’ ...
Page 190
... PIC16(L)F1938/9 NOTES: DS41574A-page 190 Preliminary 2011 Microchip Technology Inc. ...
Page 191
... T1CKI Note 1: ST Buffer is high speed type when using T1CKI. 2: Timer1 register increments on rising edge. 3: Synchronize does not operate while in Sleep. 2011 Microchip Technology Inc. PIC16(L)F1938/9 • Gate Toggle mode • Gate Single-pulse mode • Gate Value Status • Gate Event Interrupt Figure 21 block diagram of the Timer1 module ...
Page 192
... T1CKI is low. T1OSCEN Instruction Clock (F OSC x System Clock (F ) OSC x External Clocking on T1CKI Pin 0 External Clocking on T1CKI Pin 0 Capacitive Sensing Oscillator x Preliminary internal clock source is selected, the system clock or they can run Clock Source /4) 2011 Microchip Technology Inc. ...
Page 193
... When switching from synchronous to Note: asynchronous operation possible to skip an increment. When switching from asynchronous to synchronous operation possible to produce an additional increment. 2011 Microchip Technology Inc. PIC16(L)F1938/9 21.5.1 READING AND WRITING TIMER1 IN ASYNCHRONOUS COUNTER MODE Reading TMR1H or TMR1L while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware) ...
Page 194
... TMR1GIE bit in the PIE1 register is set, then an interrupt will be recognized. The TMR1GIF flag bit operates even when the Timer1 gate is not enabled (TMR1GE bit is cleared). Preliminary Figure 21-5 for timing details. Figure 21-6 for timing 2011 Microchip Technology Inc. ...
Page 195
... TMR1 Enabled Note 1: Arrows indicate counter increments Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. 2011 Microchip Technology Inc. PIC16(L)F1938/9 Timer1 oscillator will continue to operate in Sleep regardless of the T1SYNC bit setting. ...
Page 196
... PIC16(L)F1938/9 FIGURE 21-3: TIMER1 GATE ENABLE MODE TMR1GE T1GPOL T1G_IN T1CKI T1GVAL TIMER1 N FIGURE 21-4: TIMER1 GATE TOGGLE MODE TMR1GE T1GPOL T1GTM T1G_IN T1CKI T1GVAL TIMER1 DS41574A-page 196 Preliminary 2011 Microchip Technology Inc ...
Page 197
... TIMER1 GATE SINGLE-PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF 2011 Microchip Technology Inc. PIC16(L)F1938/9 Cleared by hardware on falling edge of T1GVAL Set by hardware on falling edge of T1GVAL Preliminary Cleared by software DS41574A-page 197 ...
Page 198
... TIMER1 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ Set by software DONE Counting enabled on rising edge of T1G T1G_IN T1CKI T1GVAL TIMER1 N Cleared by software TMR1GIF DS41574A-page 198 Set by hardware on falling edge of T1GVAL Preliminary 2011 Microchip Technology Inc. Cleared by hardware on falling edge of T1GVAL Cleared by software ...
Page 199
... This bit is ignored bit 1 Unimplemented: Read as ‘0’ bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Clears Timer1 gate flip-flop 2011 Microchip Technology Inc. PIC16(L)F1938/9 R/W-0/u R/W-0/u R/W-0/u T1OSCEN T1SYNC U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ...
Page 200
... Comparator 1 optionally synchronized output (SYNCC1OUT Comparator 2 optionally synchronized output (SYNCC2OUT) DS41574A-page 200 R/W-0/u R/W/HC-0/u R-x/x T1GSPM T1GGO/ T1GVAL DONE U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets HC = Bit is cleared by hardware Preliminary R/W-0/u R/W-0/u T1GSS<1:0> bit 0 2011 Microchip Technology Inc. ...