PIC16LF1933-E/MV Microchip Technology, PIC16LF1933-E/MV Datasheet - Page 302

• Manufacturer Part Number: PIC16LF1933-E/MV
• Description: IC MCU 8BIT 7KB FLASH 28UQFN
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1933-E/MV

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 32MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-UFQFN Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC16(L)F1933
25.4.2.3
The operation of the Synchronous Master and Slave
modes is identical
Master
• Sleep
• CREN bit is always set, therefore the receiver is
• SREN bit, which is a “don’t care” in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
TABLE 25-10: SUMMARY OF REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE
DS41575A-page 302
BAUDCON
INTCON
PIE1
PIR1
RCREG
RCSTA
TRISC
TXSTA
Legend: — = unimplemented read as ‘0’. Shaded cells are not used for synchronous slave reception.
never Idle
Name
Reception”), with the following exceptions:
*
Page provides register information.
EUSART Synchronous Slave
Reception
TMR1GIE
EUSART Receive Data Register
TMR1GIF
ABDOVF
TRISC7
CSRC
SPEN
Bit 7
RECEPTION
GIE
(Section 25.4.1.5 “Synchronous
TRISC6
RCIDL
PEIE
ADIE
ADIF
Bit 6
RX9
TX9
TMR0IE
TRISC5
SREN
TXEN
RCIE
RCIF
Bit 5
—
TRISC4
Preliminary
CREN
SYNC
SCKP
INTE
TXIE
Bit 4
TXIF
ADDEN
TRISC3
SENDB
BRG16
SSPIE
SSPIF
IOCIE
25.4.2.4
1.
2.
3.
4.
5.
6.
7.
8.
9.
Bit 3
Set the SYNC and SPEN bits and clear the
CSRC bit.
Clear the ANSEL bit for both the CK and DT pins
(if applicable).
If interrupts are desired, set the RCIE bit of the
PIE1 register and the GIE and PEIE bits of the
INTCON register.
If 9-bit reception is desired, set the RX9 bit.
Set the CREN bit to enable reception.
The RCIF bit will be set when reception is
complete. An interrupt will be generated if the
RCIE bit was set.
If 9-bit mode is enabled, retrieve the Most
Significant bit from the RX9D bit of the RCSTA
register.
Retrieve the 8 Least Significant bits from the
receive FIFO by reading the RCREG register.
If an overrun error occurs, clear the error by
either clearing the CREN bit of the RCSTA
register or by clearing the SPEN bit which resets
the EUSART.
TMR0IF
CCP1IE
CCP1IF
TRISC2
BRGH
FERR
Bit 2
—
Synchronous Slave Reception
Set-up:
TMR2IE
TMR2IF
TRISC1
OERR
TRMT
WUE
INTF
Bit 1
 2011 Microchip Technology Inc.
TMR1IE
TMR1IF
ABDEN
TRISC0
IOCIF
RX9D
TX9D
Bit 0
Register
on Page
280*
286
285
129
284
86
87
90