ADM00310 Microchip Technology, ADM00310 Datasheet - Page 37

• Manufacturer Part Number: ADM00310
• Description: BOARD EVAL FOR MCP3903 AFE
• Manufacturer: Microchip Technology
• Series: -r

Specifications of ADM00310

• Design Resources: MCP3903 Eval Brd BOM MCP3903 Eval Brd Schematic
• Main Purpose: Interface, Analog Front End (AFE)
• Embedded: Yes, MCU, 16-Bit
• Utilized Ic / Part: MCP3903, PIC24F, PIC24H, dsPIC33, MCP2200
• Primary Attributes: -
• Secondary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

7.0
The addresses associated with the internal registers
are listed below. All registers are 24 bits long and can
be addressed separately. A detailed description of the
registers follows.
TABLE 7-1:
The following table shows how the internal address
counter will loop on specific register groups and types.
TABLE 7-2:
© 2011 Microchip Technology Inc.
CHANNEL 1
CHANNEL 2
CHANNEL 4
CHANNEL 5
CHANNEL 0
CHANNEL 3
Address
Function
STATUS/
CONFIG
PHASE
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
GAIN
MOD
COM
INTERNAL REGISTERS
Address
STATUS/COM
0x0A
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
INTERNAL REGISTER SUMMARY
CONTINUOUS READ
OPTIONS, LOOPING ON
INTERNAL ADDRESSES
CONFIG
PHASE
Name
GAIN
MOD
GROUP
GROUP
GROUP
= “01”
READ<1:0>
Bits
= “10”
24
24
24
24
24
24
24
24
24
24
24
R/W
R/W Delta Sigma Modulators Output Value
R/W Phase Delay Configuration Register
R/W Gain Configuration Register
R/W Status/Communication Register
R/W Configuration Register
R
R
R
R
R
R
=“11”
Channel 0 ADC Data <23:0>, MSB first, left justified
Channel 1 ADC Data <23:0>, MSB first, left justified
Channel 2 ADC Data <23:0>, MSB first, left justified
Channel 3 ADC Data <23:0>, MSB first, left justified
Channel 4 ADC Data <23:0>, MSB first, left justified
Channel 5 ADC Data <23:0>, MSB first, left justified
.
7.1
TABLE 7-3:
The ADC Channel data output registers always contain
the most recent A/D conversion data for each channel.
These registers are read-only. They can be accessed
independently or linked together (with READ<1:0>
bits). These registers are latched when an ADC read
communication occurs. When a data ready event
occurs during a read communication, the most current
ADC data is also latched to avoid data corruption
issues. The three bytes of each channel are updated
synchronously at a DRCLK rate. The three bytes can
be accessed separately if needed, but are refreshed
synchronously. The coding is 23-bit + sign two’s
complement (see Section 5.5).
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
Name
Channel Output Registers
Description
ADC OUTPUT REGISTERS
Bits
24
24
24
24
24
24
MCP3903
Address
0x00
0x01
0x02
0x03
0x04
0x05
DS25048B-page 37
Cof
R
R
R
R
R
R