AH5012CN National Semiconductor, AH5012CN Datasheet - Page 5

• Manufacturer Part Number: AH5012CN
• Description: IC SWITCH QUAD ANALOG 16-DIP
• Manufacturer: National Semiconductor

Specifications of AH5012CN

• Function: Switch
• Circuit: 4 x SPST - NO
• On-state Resistance: 240 Ohm
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Through Hole
• Package / Case: 16-DIP (0.300", 7.62mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *AH5012CN

Applications Information
Theory of Operation
The AH series of analog switches are primarily intended for
operation in current mode switch applications i e
drains of the FET switch are held at or near ground by oper-
ating into the summing junction of an operational amplifier
Limiting the drain voltage to under a few hundred millivolts
eliminates the need for a special gate driver allowing the
switches to be driven directly by standard TTL 5V-10V
CMOS open collector 15V TTL CMOS
Two basic switch configurations are available 4 indepen-
dent switches (SPST) and 4 pole switches used for multi-
plexing (4 PST-MUX) The MUX versions such as the
AH5010 offer common drains and include a series FET op-
erated at V
feedback path in order to compensate for the ‘‘ON’’ resist-
ance of the switch FET as shown in Figure 1
The closed-loop gain of Figure 1 is
For R1
match between Q1 and Q2 Typical match between Q1 and
Q2 is 4 ohms resulting in a gain accuracy of 0 05% (for R1
Noise Immunity
The switches with the source diodes grounded exhibit im-
proved noise immunity for positive analog signals in the
e
A
R2
VCL
e
e
e
10 k )
R2
R1
R2 gain accuracy is determined by the r
GS
a
e
a
r
r
DS(ON)Q1
0V The additional FET is placed in the
DS(ON)Q2
FIGURE 2 On Leakage Current I
FIGURE 1 Use of Compensation FET
DS(ON)
the
5
‘‘OFF’’ state With V
of Q1 is clamped to about 0 7V by the diode (V
ensuring that ac signals imposed on the 10V input will not
gate the FET ‘‘ON ’’
Selection of Gain Setting Resistors
Since the AH series of analog switches are operated in cur-
rent mode it is generally advisable to make the signal cur-
rent as large as possible However current through the FET
switch tends to forward bias the source to gate junction and
the signal shunting diode resulting in leakage through these
junctions As shown in Figure 2 I
error in the current reaching the summing junction of the op
amp
Secondly the r
approaches I
at less than
Combining the criteria from the above discussion yields
or
whichever is larger
R1
min t
t
G(ON)
V
V
I
DSS
A(MAX)
A(MAX)
DSS
I
G(ON)
DS(ON)
of I
10
A practical rule of thumb is to maintain I
DSS
A
IN
D
e
of the FET begins to ‘‘round’’ as I
15V and the V
G(ON)
A
represents a finite
e
10V the source
GS
TL H 5659– 4
e
14 3V)
(2a)
(2b)
S
S