AT32UC3C0512C-ALZT Atmel, AT32UC3C0512C-ALZT Datasheet - Page 27
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AT32UC3C0512C-ALZT
Manufacturer Part Number
AT32UC3C0512C-ALZT
Description
512KB FLASH 144LQFP -40/125?C AUTO TRAY
Manufacturer
Atmel
Datasheet
1.AT32UC3C1512C-AZR.pdf
(106 pages)
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4.3.1
9166BS–AVR-02/11
Pipeline Overview
Figure 4-1.
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 28
Instruction memory controller
High Speed Bus master
Overview of the AVR32UC CPU
system
shows an overview of the AVR32UC pipeline stages.
OCD
AVR32UC CPU pipeline
High Speed
Bus master
MPU
Data memory controller
Bus slave
Speed
High
CPU Local
Power/
control
Reset
master
Bus
AT32UC3C
CPU RAM
27
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