DS2172T+ Maxim Integrated Products, DS2172T+ Datasheet - Page 4
![IC TESTER BIT ERROR RATE 32-TQFP](/photos/6/98/69820/ds2172t__sml.jpg)
DS2172T+
Manufacturer Part Number
DS2172T+
Description
IC TESTER BIT ERROR RATE 32-TQFP
Manufacturer
Maxim Integrated Products
Datasheet
1.DS2172T.pdf
(22 pages)
Specifications of DS2172T+
Function
Bit Error Rate Tester (BERT)
Interface
T1
Number Of Circuits
1
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
10mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
*
Includes
Error Counter, Pattern Generator and Detector
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
DETAILED PIN DESCRIPTION Table 1
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
SYMBOL
WR
ALE(AS)
RD
RLOS
TEST
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
BTS
V
V
V
V
INT
V
LC
TL
CS
(R/
(DS)
DD
DD
SS
SS
SS
W
)
TYPE DESCRIPTION
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
I
I
-
-
-
I
I
I
I
I
-
-
I
Transmit Load. A positive-going edge loads the pattern generator with
the contents of the Pattern Set Registers. The MSB of the repetitive or
pseudorandom pattern appears at TDATA after the third positive edge of
TCLK from asserting TL. TL is logically OR’ed with PCR.7 and should
be tied to V
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Test. Set high to 3-state all output pins (
Should be tied to V
Signal Ground. 0.0V. Should be tied to local ground plane.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Data Bus. An 8-bit multiplexed address/data bus.
Signal Ground. 0.0V. Should be tied to local ground plane.
Positive Supply. 5.0V.
Bus Type Select. Strap high to select Motorola bus timing; strap low to
select Intel bus timing. This pin controls the function of the
ALE(AS), and
function listed in parenthesis ().
Read Input (Data Strobe).
Chip Select. Must be low to read or write the port.
Address Latch Enable (Address Strobe). A positive going edge serves
to demultiplex the bus.
Write Input (Read/Write).
Alarm Interrupt. Flags host controller during conditions defined in
Status Register. Active low, open drain output.
Positive Supply. 5.0V.
Signal Ground. 0.0V. Should be tied to local ground plane.
Load Count. A positive-going edge latches the current bit and bit error
count into the user accessible BCR and BECR registers and clears the
internal count registers. LC is logically OR’ed with control bit PCR.4.
Should be tied to V
Receive Loss Of Sync. Indicates the real time status of the receive
synchronizer. Active high output.
SS
if not used. See Figure 8 for timing information.
WR
4 of 22
SS
SS
(R/
to enable all outputs.
if not used.
W
) pins. If BTS = 1, then these pins assume the
INT
, ADx, TDATA, RLOS).
RD
DS2172
(DS),