DS2187 Maxim Integrated Products, DS2187 Datasheet
DS2187
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DS2187 Summary of contents
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... DESCRIPTION The DS2187 T1/CEPT Receive Line Interface chip interfaces user equipment to North American (T1 1.544 MHz) and European (CEPT 2.048 MHz) primary rate communication networks. The device extracts clock and data from twisted pair or coax transmission media and eliminates expensive discrete components and/or manual tuning required in existing T1 and CEPT line termination electronics ...
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... DS2187 BLOCK DIAGRAM Figure 1 LINE INPUT Input signals are coupled to the DS2187 via a 1:2 center-tapped transformer as shown in Figure 2. For T1 applications, R1 and R2 must be 200 ohms in order to properly terminate the line at 100 ohms. R1 and R2 are set at 150 or 240 ohms for CEPT applications. Special internal circuitry of the RTIP and RRING ...
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PIN DESCRIPTION Table 1 PIN SYMBOL TYPE 1 AVDD 2 RAIS 3 ZCSEN 4 LCAP 5 RCLKSEL 6 RTIP 7 RRING 8 LOCK 9 AVSS 10 DVSS 11 RCLK 12 RNEG 13 RPOS BPV 16 AIS 17 ...
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SYSTEM LEVEL INTERCONNECT Figure 2 OUTPUT TIMING Figure ...
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... AVSS, DVDD and DVSS) should be connected to system analog and digital supplies. If separate system supplies do not exist, the appropriate supply pins can be tied together. Tying the analog and digital supplies together on the DS2187 will not degrade its performance, provided the power supply is sufficiently decoupled. ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the ...
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ANALOG ELECTRICAL CHARACTERISTICS PARAMETER Clock Acquisition RTIP, RRING Minimum Sensitivity FLL Loop Bandwidth Capture Range Input Jitter Tolerance NOTES: 1. Time from reappearance of a valid signal at RPOS and RNEG to a LOCK=1. 2. Minimum peak voltage necessary for ...
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NOTES applications (RCLKSEL=0). 2. CEPT applications (RCLKSEL=1). 3. Minimum and maximum limits shown reflect changes in DPLL divide ratio as required to track jitter. AC TIMING DIAGRAM Figure ...
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... DS2187 RECEIVE LINE INTERFACE 18-PIN DIP PKG 18-PIN DIM MIN MAX A IN 0.890 0.920 0.240 0.260 MM 6.10 6. 0.120 0.140 MM 3.05 3. 0.300 0.325 MM 7.62 8. 0.015 0.040 MM 0.38 1. 0.120 0.140 MM 3.04 3. 0.090 0.110 MM 2.23 2. 0.320 0.370 MM 8.13 9. 0.008 0.012 MM 0.20 0. 0.015 0.021 MM 0.38 ...
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... DS2187S RECEIVE LINE INTERFACE 20-PIN SOIC PKG 18-PIN DIM MIN MAX A IN 0.500 0.511 MM 12.70 12. 0.290 0.300 MM 7.37 7. 0.089 0.095 MM 2.26 2. 0.004 0.012 MM 0.102 0. 0.094 0.105 MM 2.38 2. 0.050 BSC MM 1.27 BSC H IN 0.398 0.416 MM 10.11 10. 0.009 0.013 MM 0.229 0. 0.013 0.019 MM 0.33 ...