SI3216-C-FT Silicon Laboratories Inc, SI3216-C-FT Datasheet
SI3216-C-FT
Specifications of SI3216-C-FT
Available stocks
Related parts for SI3216-C-FT
SI3216-C-FT Summary of contents
Page 1
... The Si3216’s wideband codec provides expanded audio band ( kHz), 16 kHz sampling rate, and increased dynamic range for improved audio quality over traditional telephony codecs ...
Page 2
... Si3216 2 Rev. 1.0 ...
Page 3
... Pin Descriptions: Si3216 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 6. Pin Descriptions: Si3201 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 7. Ordering Guides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 8. Package Outline: 38-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 9. Package Outline: 38-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 10. Package Outline: 16-Pin ESOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 11. Silicon Labs Si3216 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Rev. 1.0 Si3216 Page ...
Page 4
... Exposure to absolute maximum rating conditions for extended periods may affect device reliability. º 2. Operation above 125 C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3216 DDD DDA1 DDA2 I IN ...
Page 5
... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3216 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used ...
Page 6
... Si3216 Table 3. AC Characteristics—Wideband Audio Mode: Si3216 ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter TX/RX Performance—Wideband Audio Mode Overload Level 1 Single Frequency Distortion Signal-to-(Noise + Distortion) Ratio Audio Tone Generator 2 Signal-to-Distortion Ratio Intermodulation Distortion ...
Page 7
... Table 3. AC Characteristics—Wideband Audio Mode: Si3216 (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Noise Performance—Wideband Audio Mode 3 Idle Channel Noise PSRR from V DDA PSRR from V DDD PSRR from V BAT Longitudinal Performance—Wideband Audio Mode ...
Page 8
... Si3216 (dB 100 –1 –4.5 Figure 1. Transmit and Receive Path Attenuation Distortion—Wideband Mode (ms 0.25 50 100 Figure 2. Transmit and Receive Path Group Delay Distortion—Wideband Mode 8 6.4k 7k 300 4k 6.4k Rev. 1.0 (Hz –25 –45 (Hz) 7k ...
Page 9
... Hz – –0.017 All gain settings –0. 3.3/5 V ±5% DDA DDA 200 Hz–3.4 kHz 200 Hz–3.4 kHz – Assumes ideal line impedance matching. RING Rev. 1.0 Si3216 Min Typ Max Unit 2.5 — — V — — –45 — — 45 — — ...
Page 10
... Si3216 Table 4. AC Characteristics—Narrowband Audio Mode (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Noise Performance—Narrowband Audio Mode 4 Idle Channel Noise PSRR from VDDA PSRR from V DDD PSRR from V BAT Longitudinal Performance—Narrowband Audio Mode ...
Page 11
... Figure 3. Transmit and Receive Path SNDR—Narrowband Mode Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 4. Overload Compression Performance Rev. 1.0 Acceptable Region Si3216 11 ...
Page 12
... Si3216 Figure 5. Transmit Path Frequency Response—Narrowband Mode 12 Typical Response Typical Response Rev. 1.0 ...
Page 13
... Figure 6. Receive Path Frequency Response—Narrowband Mode Rev. 1.0 Si3216 13 ...
Page 14
... Si3216 Figure 7. Transmit Group Delay Distortion—Narrowband Mode Figure 8. Receive Group Delay Distortion—Narrowband Mode 14 Rev. 1.0 ...
Page 15
... REN load; sine wave 160 –75 V LOOP BAT Programmable in Indirect OS Register 6 Crest factor = 1 Accuracy of ON/OFF Times CAL to CAL Bit At Power Threshold = 300 mW Rev. 1.0 Si3216 Min Typ Max Unit 0 — 160 –10 — –4 — ...
Page 16
... Si3216 Table 6. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity INLE (6-bit resolution) Gain Error (voltage) Gain Error (current) Table 7. Si321x DC Characteristics 4. °C for K-Grade, – °C for B-Grade) ...
Page 17
... BAT Sleep (RESET = 0) BAT Open (DCOF = 1) Active on-hook ETBO = Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA LIM Ground-start Ringing PK_RING PK sinewave ringing, REN = 1 When using Si3201 x V BAT BAT Rev. 1.0 Si3216 1 2 Max Typ Typ 0.1 0.13 0 — ...
Page 18
... Si3216 Table 10. Switching Characteristics—General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are ...
Page 19
... Figure 9. SPI Timing Diagram = Test Symbol Conditions 1 dty t jitter su1 su2 t h2 Rev. 1.0 Si3216 Units Min Typ Max — 0.256 — MHz — 0.512 — MHz — 0.768 — MHz — 1.024 — MHz — 1.536 — MHz — ...
Page 20
... Table 18 or from App Note 45. R21 2. Only one component per system needed All circuit ground should have a single-point connection to the ground plane. 1 R29 4. Si3201 bottom-side exposed pad should be electrically and thermally connected to bulk ground plane. Figure 11. Si3216(M) Application Circuit Using Si3201 ...
Page 21
... Table 13. Si3216(M) + Si3201 External Component Values Component (s) C1,C2 10 µ Ceramic Low Leakage Electrolytic, C3,C4 220 nF, 100 V, X7R, ±20% C5,C6 22 nF, 100 V, X7R, ±20% C15,C16,C17,C24 C18,C19 4.7 µF Ceramic X7R, ±20% C26 0.1 µF, 100 V, X7R, ±20% C30, C31 10 µ Electrolytic, ±20% ...
Page 22
... Only one component per system needed. 3. All circuit grounds should have a single- point connection to the ground plane. 4. Optional components to improve idle channel noise. Figure 12. Si3216(M) Typical Application Circuit Using Discrete Line Interface Circuit Table 14. Si3216(M) External Component Values Component C1,C2 10 µ Ceramic/Tantalum Low Leakage 220 nF, 100 V, X7R, ...
Page 23
... Table 14. Si3216(M) External Component Values (Continued) 200 k , 1/10 W, 1% R1,R3 100 k , 1/10 W, 1% R2,R4,R5, R102,R104,R105 80.6 , 1/4 W, 1% R6,R7 4.7 k , 1/10 W, 1% R8,R9 10 , 1/10 W, 5% R10,R11 5.1 k , 1/10 W, 5% R12,R13 40.2 k , 1/10 W, 1% R14,R26* 243 ...
Page 24
... Si3216 Table 15. Si321x BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10* C14* C25* R16 R17 1/10 W, ±5% (See “AN45: Design Guide for The Si3210 DC- DC Converter” or Table 20 for value selection) R18 1/4 W, ±5% (See AN45 or Table 20 for value selection) R19,R20 1/10 W, ± ...
Page 25
... Q6 C7 5551 CRBN 100 nF R6 R13 RTE RTBN 80.6 5.1k Rev. 1.0 Si3216 Supplier Panasonic Murata, Johanson, Novacap, Venkel Panasonic Murata, Johanson, Novacap, Venkel Belfuse SSQ Series General Semi ES1D; Central Semi CMR1U-02 Coiltronic CTX01-15275; Datatronics SM76315; Midcom 31353R-02 Intl Rect. IRLL014N; Intersil HUF76609D3S ...
Page 26
... Si3216 Table 17. Si321x Optional Bias Component Values Component 100 nF, 100 V, X7R, 20% C7,C8 3.0 k , 1/10 W, 5% R23,R24 The subcircuit above can be substituted into any of the ProSLIC solutions as an optional bias circuit for Q5, Q6. For this optional subcircuit, C7 and C8 are different in voltage and capacitance to the standard circuit. R23 and R24 are additional components ...
Page 27
... The Si3216 is ideal for Customer Premise Equipment (CPE) where enhanced audio quality is required. Unlike most monolithic SLICs, the ProSLIC does not require externally-supplied, high-voltage supplies ...
Page 28
... Si3216 2.1.2. Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses either an Si3201 linefeed interface IC or low-cost external components to control the high voltages required for subscriber line interfaces. Figure simplified illustration of the linefeed control loop circuit for TIP or RING and the external components used. ...
Page 29
... TIP RING TIP tri-stated, RING active; used for ground start Ringing waveform applied to TIP and RING V > V RING TIP V > audio signal paths enabled RING TIP RING tri-stated, TIP active Rev. 1.0 Si3216 Battery Sense DC Em itter Sense BAT V BAT 29 ...
Page 30
... Si3216 Table 23. Measured Real Time Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage Sense BAT Transistor 1 Current Sense Transistor 2 Current Sense Transistor 3 Current Sense ...
Page 31
... Bits corre- spond Q6, N/A respectively Bits corre- spond Q6, N/A respectively 0 = manual mode 1 = enter Open N/A state upon power alarm Rev. 1.0 Si3216 Register Location* Bits PWRMP[2:0] Direct Register 76 PWROM[7:0] Direct Register 77 PPT12[7:0] Indirect Register 19 PPT34[7:0] Indirect Register 20 PPT56[7:0] Indirect Register 21 NQ12[7:0] ...
Page 32
... Si3216 LCS Input ISP_OUT Signal LVS Processor LFS LCVE 2.1.6. Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during On-Hook Transmission or On- Hook Active states. The ProSLIC performs loop closure detection digitally using its on-chip monitor A/D converter ...
Page 33
... DC For this solution, a PNP power BJT (Q7) switches the current flow through low ESR inductor L1. The Si3216 uses the DCDRV and DCFF pins to switch Q7 on and off. DCDRV controls Q7 through NPN BJT Q8. DCFF is ac-coupled to Q7 through capacitor C10 to assist R16 in turning off Q7 ...
Page 34
... Si3216 power supply (number of REN supported). For this solution, an n-channel power MOSFET (M1) switches the current flow through a power transformer T1 specified in “AN45: Design Guide for the Si3210/15/16 DC-DC Converter” and includes several taps on the primary side to facilitate a wide range of input voltages. The “M” version of the ProSLIC must be ...
Page 35
... TIP RING BAT Range Resolution N/A N/A N/A N 15.564 µs 61.035 1.892 µs) + 61.035 –94 –94 – 1 –13.5 V Rev. 1.0 Si3216 R Constant V Region LOOP V TIP RING BAT Register Bit Location DCOF Direct Register 14 DCCAL Direct Register 93 DCN[7:0] Direct Register 92 ...
Page 36
... Si3216 2.2.5. DC-DC Converter Enhancements The ProSLIC supports two selectable enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5). The second enhancement is an audio band filter that removes audio band noise from the dc-dc converter control loop ...
Page 37
... REL bit (direct Register 32, bit 6), which enables reloading of the OSC1, OSC1X, and OSC1Y registers at the expiration of the active timer (OAT1). Rev. 1.0 Si3216 phase frequency-shift keying (FSK) 37 ...
Page 38
... Si3216 Table 28. Associated Tone Generator Registers Parameter Oscillator 1 Frequency Coefficient Oscillator 1 Amplitude Coefficient Oscillator 1 initial phase coefficient Oscillator 1 Active Timer Oscillator 1 Inactive Timer Oscillator 1 Control Parameter Oscillator 2 Frequency Coefficient Oscillator 2 Amplitude Coefficient Oscillator 2 initial phase coefficient Oscillator 2 Active Timer Oscillator 2 Inactive Timer ...
Page 39
... RAT, the ProSLIC turns off the ringing waveform and goes to the on-hook transmission state. Upon expiration of RIT, ringing again initiates. This process continues as long as the two timers are enabled and the Linefeed Control register is set to the Ringing state. Rev. 1.0 Si3216 circuit with programmable the ringing waveform ...
Page 40
... Si3216 Table 29. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing dc voltage offset ...
Page 41
... V OVR where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for V 018Ch following equation: Rev. 1.0 Si3216 , is added to the ringing signal when ROFF V 15 ROFF ----------------- - ROFF = 2 96 BAT BATH setting for a particular desired peak ringing ...
Page 42
... Si3216 BATH AC,PK ROFF The ProSLIC is designed to create a fully-balanced ringing waveform, meaning that the TIP and RING common mode voltage TIP RING voltage is referred and is automatically CM_RING set to the following: V – V BATH -------------------------------------- - V = CM_RING indirect register, which provides the CMR headroom by the ringing waveform with respect to the V rail ...
Page 43
... A-law or µ-law compression block. In narrowband mode, µ-law or A-law compression can be selected to reduce the data stream word width to 8 bits. Rev. 1.0 Si3216 Location Direct Register 19 Direct Register 22 Direct Register 70 Indirect Register 16 ...
Page 44
... Si3216 44 Rev. 1.0 ...
Page 45
... XAC creates the imaginary portion of the ac impedance. G that models the desired impedance value to the subscriber loop. The differential ac current is fed to the Rev. 1.0 Si3216 network (XAC), and a ) (See Figure 24.) RAC m then creates a current ...
Page 46
... These bits are set when an interrupt is pending for the associated STIPAC resource. Three interrupt enable registers also contain 1 bit for each interrupt function. In the case of the interrupt Si3216 enable registers, the bits are active high. Refer to the appropriate functional SRINGAC operational details of the interrupt functions ...
Page 47
... SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered. Don't Care High Impedance Figure 26. Serial Write 8-Bit Mode Don't Care Figure 27. Serial Read 8-Bit Mode Rev. 1.0 Si3216 Don't Care ...
Page 48
... Si3216 SDO CPU CS SDI Chip Select Byte SCLK SDI0 SDI1 – SDI2 – – SDI3 – – – Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. ...
Page 49
... TXS and RXS registers. For the Si3216 in wideband mode (WBE = 1, PCMF = 11, and PCMT = 1), TXS and RXS set the correct starting point of the data for the first timeslot within the 8 kHz frame, and the second timeslot is set to follow 62.5 µ ...
Page 50
... Si3216 Table 32. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 __________________ Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits. 50 Value at Segment Endpoints Digital Code 8159 10000000 ...
Page 51
... Digital code includes inversion of all even numbered bits. Value at segment endpoints Digital Code 4096 3968 1010101 2176 2048 1010010 1088 1024 1011010 544 512 1000010 272 256 1001010 136 128 1110010 1111010 1101010 1 Rev. 1.0 Si3216 1,2 Decode Level 4032 b 2112 b 1056 b 528 b 264 b 132 ...
Page 52
... Si3216 3. Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 PCM Receive Start Count—Low Byte 5 PCM Receive Start Count— ...
Page 53
... OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ETBE VOV MNCM MNDIF SPDS Rev. 1.0 Si3216 Bit 3 Bit 2 Bit 1 Bit 0 IAS O1TIE O1E O1SO[1:0] O2TIE O2E O2SO[1:0] RTIE ROE RVO TSWS FSKDAT LF[2:0] ETBO[1:0] ETBA[1:0] ...
Page 54
... Si3216 Table 34. Direct Register Summary (Continued) Register Name 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High Battery Voltage 75 Low Battery Voltage 76 Power Monitor Pointer 77 Line Power Output ...
Page 55
... DC Peak Current Moni- tor Calibration Result 108 Enhancement Enable Bit 7 Bit 6 Bit 5 Bit 4 CAL CALSP CALR CALM1 CALMG1[3:0] DACOF[7:0] ILIMEN FSKEN DCSU Rev. 1.0 Si3216 Bit 3 Bit 2 Bit 1 Bit 0 CALT CALD CALC CALIL CALM2 CALDAC CALADC CALGMR[4:0] CALGMT[4:0] CALGD[4:0] CALGC[4:0] CALGIL[3:0] ...
Page 56
... Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification. Note: PNI[2:0] can be read in direct register Si3216 01 = Reserved 10 = Reserved 11 = Si3216M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc ...
Page 57
... PNI2 Part Number Identification 2. Note: PNI[2:0] can be read in direct Register Si3210, Si3211 family Si3216 family. 6 WBE Wideband Enable Narrowband (200 Hz–3.4 kHz) audio filtering at 8 kHz sample rate Wideband (50 Hz–7 kHz) audio filtering at 16 kHz sample rate when PCMF = 11 and PCMT = 1 ...
Page 58
... Si3216 Register 2. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data trans- mission begins. See Figure 29 on page 49. ...
Page 59
... Part Number Identification. Note: PNI[2] can be read in direct Register 1. PNI[1:0] can be read in direct Register 0. 000 = Reserved 001 = Reserved 010 = Reserved 011 = Reserved 4:0 Reserved Read returns zero Function Function 100 = Si3216 101 = Reserved 110 = Reserved 111 = Si3216M Rev. 1.0 Si3216 D1 D0 RXS[9:8] R ...
Page 60
... Si3216 Register 8. Audio Path Loopback Control Bit D7 D6 Name Type Reset settings = 0000_0010 Bit Name 7:3 Reserved Read returns zero. 2 ALM2 Analog Loopback Mode 2. (See Figure 24 on page 44 Full analog loopback mode disabled Full analog loopback mode enabled. 1 DLM Digital Loopback Mode. (See Figure 24 on page 44 Digital loopback disabled ...
Page 61
... Receive signal passed Receive signal muted. 3:2 ATX[1:0] Analog Transmit Path Gain –3 3 ATX gain = 0 dB; analog transmit path muted. 1:0 ARX[1:0] Analog Receive Path Gain –3 3 Analog receive path muted RXM ATX[1:0] R/W R/W Function Rev. 1.0 Si3216 D1 D0 ARX[1:0] R/W 61 ...
Page 62
... Si3216 Register 10. Two-Wire Impedance Synthesis Control Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5:4 CLC[1:0] Line Capacitance Compensation Off Reserved 3 TISE Two-Wire Impedance Synthesis Enable Two-wire impedance synthesis disabled Two-wire impedance synthesis enabled. ...
Page 63
... Off 3 Reserved Read returns zero. 2:0 HYBA[2:0] Audio Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = –1.02 dB 101 = –1.94 dB 110 = –2.77 dB 111 = Off Function Rev. 1.0 Si3216 D1 D0 HYBA[2:0] R/W 63 ...
Page 64
... Si3216 Register 14. Powerdown Control 1 Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4 DCOF DC-DC Converter Power-Off Control Automatic power control Override automatic control and force dc-dc circuitry off. 3 PFR PLL Free-Run Control Automatic free-run control. ...
Page 65
... Manual power control; GMON controls on/off state. 0 GMON Transconductance Amplifier On/Off Power Control. When GMM = Analog to digital converter powered off Analog to digital converter powered on. GMON has no effect when GMM = ADCON DACM DACON R/W R/W R/W Function Rev. 1.0 Si3216 D1 D0 GMM GMON R/W R/W 65 ...
Page 66
... Si3216 Register 18. Interrupt Status 1 Bit D7 D6 Name RGIP Type R/W Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIP Ringing Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 4 RGAP Ringing Active Timer Interrupt Pending. ...
Page 67
... Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 RTIP Ring Trip Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending Q3AP Q2AP Q1AP R/W R/W R/W Function Rev. 1.0 Si3216 D1 D0 LCIP RTIP R/W R/W 67 ...
Page 68
... Si3216 Register 20. Interrupt Status 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writing 1 to this bit clears a pending interrupt. ...
Page 69
... Oscillator 2 Active Timer Interrupt Enable Interrupt masked Interrupt enabled. 1 O1IE Oscillator 1 Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 0 O1AE Oscillator 1 Active Timer Interrupt Enable Interrupt masked Interrupt enabled RGAE O2IE O2AE R/W R/W R/W Function Rev. 1.0 Si3216 D1 D0 O1IE O1AE R/W R/W 69 ...
Page 70
... Si3216 Register 22. Interrupt Enable 2 Bit D7 D6 Name Q6AE Q5AE Q4AE Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AE Power Alarm Q6 Interrupt Enable Interrupt masked Interrupt enabled. 6 Q5AE Power Alarm Q5 Interrupt Enable Interrupt masked Interrupt enabled. 5 Q4AE Power Alarm Q4 Interrupt Enable. ...
Page 71
... Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved Read/write bit with no function Function Rev. 1.0 Si3216 D1 D0 INDE R/W 71 ...
Page 72
... Si3216 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate— ...
Page 73
... IAA at the next indirect memory update (a read operation). Register 31. Indirect Address Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 IAS Indirect Access Status indirect memory access pending Indirect memory access pending IAA[7:0] R/W Function Function Rev. 1.0 Si3216 IAS R 73 ...
Page 74
... Si3216 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL OZ1 Type R R/W R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output signal active. 6 REL Oscillator 1 Automatic Register Reload. This bit should be set for FSK signaling Oscillator 1 will stop signaling after inactive timer expires. ...
Page 75
... Enable timer. 2 O2E Oscillator 2 Enable Disable oscillator Enable oscillator. 1:0 O2SO[1:0] Oscillator 2 Signal Output Routing Unassigned path (output not connected Assign to transmit path Assign to receive path Assign to both paths O2TAE O2TIE O2E R/W R/W R/W Function Rev. 1.0 Si3216 D1 D0 O2SO[1:0] R/W 75 ...
Page 76
... Si3216 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing oscillator output signal active. 6 Reserved Read returns zero. 5 RDAC Ringing Signal DAC/Linefeed Cross Indicator. For ringing signal start and stop, output to TIP and RING is suspended to ensure conti- nuity with dc linefeed voltages ...
Page 77
... Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[7:0] Oscillator 1 Inactive Timer. LSB = 125 µ OAT1[7:0] R/W Function OAT1[15:8] R/W Function OIT1[7:0] R/W Function Rev. 1.0 Si3216 ...
Page 78
... Si3216 Register 39. Oscillator 1 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT1[15:8] Oscillator 1 Inactive Timer. Register 40. Oscillator 2 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. ...
Page 79
... OIT2[15:8] Oscillator 2 Inactive Timer. Register 48. Ringing Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[7:0] Ringing Active Timer. LSB = 125 µ OIT2[7:0] R/W Function OIT2[15:8] R/W Function RAT[7:0] R/W Function Rev. 1.0 Si3216 ...
Page 80
... Si3216 Register 49. Ringing Oscillator Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[15:8] Ringing Active Timer. Register 50. Ringing Oscillator Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[7:0] Ringing Inactive Timer. ...
Page 81
... Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps Function LCD[7:0] Function Rev. 1.0 Si3216 D1 D0 FSKDAT R ...
Page 82
... Si3216 Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual real time linefeed state. Automatic operations may cause actual linefeed state to deviate from the state defined by linefeed register (e.g., when linefeed equals Ringing state, LFS will equal on-hook transmission state during ringing silent period and Ringing state during ring burst) ...
Page 83
... ETBA[1:0] External Transistor Bias Levels—Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit Reserved ETBE ETBO[1:0] R/W R/W Function Rev. 1.0 Si3216 D1 D0 ETBA[1:0] R/W 83 ...
Page 84
... Si3216 Register 66. Battery Feed Control Bit D7 D6 Name Type Reset settings = 0000_0011 Bit Name 7:5 Reserved Read returns zero. 4 VOV Overhead Voltage Range Increase. (See Figure 19 on page 35.) This bit selects the programmable range for 13 FVBAT V Manual Setting. BAT 0 = Normal operation. ...
Page 85
... Automatic/Manual Loop Closure Detect Manual mode Enter off-hook Active state automatically upon loop closure detect. 0 AOPN Power Alarm Automatic/Manual Detect Manual mode Enter Open state automatically upon power alarm SPDS AORD R/W R/W Function Rev. 1.0 Si3216 D1 D0 AOLD AOPN R/W R/W 85 ...
Page 86
... Si3216 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. The state of this bit reflects the real time output of ring trip and loop closure detect circuits before debouncing ...
Page 87
... Name 7:3 Reserved Read returns zero. 2:0 ILIM[2:0] Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07 steps RTDI[6:0] R/W Function Function Rev. 1.0 Si3216 ILIM[2:0] R/W 87 ...
Page 88
... Si3216 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit sets the on-hook line voltage polarity ( –V TIP –V TIP 5:0 VOC[5:0] On-Hook Line Voltage ...
Page 89
... VBATH[5:0] R/W Function . The value may be set between 0 V (0x00) and –94.5 V (0x3F VBATL[5:0] R/W Function . The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V Rev. 1.0 Si3216 D1 D0 must be greater than or BATH D1 D0 must be greater than or BATH 89 ...
Page 90
... Si3216 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read power output. The power of the selected transistor is read in the PWROM register. ...
Page 91
... Negative loop current (reverse direction). 5:0 LCS[5:0] Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range 78. 1.25 mA steps LVS[5:0] R Function > TIP RING < TIP RING LCS[5:0] R Function Rev. 1.0 Si3216 D1 D0 – TIP RING – The TIP RING ...
Page 92
... Si3216 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the real time voltage at TIP with respect to ground. The range (0x00) to –95.88 V (0xFF) in. 376 V steps. Register 81. RING Voltage Sense ...
Page 93
... Transistor 2 Current Sense. This register reports the real time current through Q2. The range (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current VBATS2[7:0] R Function IQ1[7:0] R Function IQ2[7:0] R Function Rev. 1.0 Si3216 D1 D0 with respect BAT ...
Page 94
... Si3216 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the real time current through Q3. The range (0x00) to 9.59 mA (0xFF) in 37.6 µA steps. Register 87. Transistor 4 Current Sense Bit D7 D6 ...
Page 95
... This register sets the PWM period for the dc-dc converter. The range is 3.906 µs (0x40) to 15.564 µs (0xFF) in 61.035 ns steps. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906–7.751 µs, used for MOSFET transistor switching (Si3216M). 11.719–15.564 µs, used for BJT transistor switching (Si3216). D5 ...
Page 96
... DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3216 are offered to support the two relationships DCFF pin polarity is opposite of DCDRV pin (Si3216 DCFF pin polarity is same as DCDRV pin (Si3216M). ...
Page 97
... Common Mode DAC Gain Calibration Normal operation or calibration complete Calibration enabled or in progress. 0 CALIL I Calibration. LIM 0 = Normal operation or calibration complete Calibration enabled or in progress CALR CALT CALD R/W R/W R/W Function BAT Rev. 1.0 Si3216 D1 D0 CALC CALIL R/W R/W settling at the beginning of the 97 ...
Page 98
... Si3216 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1110 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or in progress. 3 CALM2 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or in progress. ...
Page 99
... Register 100. Differential Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGD[4:0] Differential DAC Gain Calibration Result CALGMR[4:0] R/W Function CALGMT[4:0] R/W Function CALGD[4:0] R/W Function Rev. 1.0 Si3216 ...
Page 100
... Si3216 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result Bit D7 D6 Name ...
Page 101
... Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result DACP DACN R/W R/W Function DACOF[7:0] R/W Function CMDCPK[3:0] Function Rev. 1.0 Si3216 D1 D0 ADCP ADCN R/W R R/W 101 ...
Page 102
... Si3216 Register 108. Enhancement Enable Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W R/W R/W Reset settings = 0000_0000 Bit Name 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time linefeed state. ...
Page 103
... Voice band squelch enabled. 0 HYSTEN Loop Closure Hysteresis Enable. When enabled, this bit allows hysteresis to the loop closure calculation. The upper and lower hysteresis thresholds are defined by Indirect Registers 28 and 43, respectively Loop closure hysteresis disabled Loop closure hysteresis enabled. Function Rev. 1.0 Si3216 103 ...
Page 104
... For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition, an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer. The indirect memory map is different from what is described in the data sheet. The indirect memory map is as follows: Table 35. Si3210 to Si3216 Indirect Register Cross Reference Si3210 Si3216 Indirect ...
Page 105
... Table 38. Digital Programmable Gain/Attenuation Indirect Registers Summary Addr. D15 D14 D13 D12 D11 13 14 D10 RCO[15:0] RNGX[15:0] RNGY[15:0] Description – ringing waveform. The range 94 TIP RING D10 DACG[11:0] ADCG[11:0] Rev. 1.0 Si3216 Reference Page 105 ...
Page 106
... Si3216 Table 39. Digital Programmable Gain/Attenuation Indirect Registers Description Addr. 13 Receive Path Digital to Analog Converter Gain/Attenuation. This register sets gain/attenuation for the receive path. The digitized signal is effectively mul- tiplied by DACG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain ...
Page 107
... This register defines the positive common mode voltage threshold. Exceeding this threshold enables a wider bandwidth of dc linefeed control for faster settling times. The range is 0–23.625 V in 0.375 V steps. D10 CML[5:0] CMH[5:0] NCLR[12:0] NRTP[12:0] NQ12[12:0] NQ34[12:0] NQ56[12:0] Description Rev. 1.0 Si3216 Reference Page 32 42 107 ...
Page 108
... Si3216 Table 41. SLIC Control Indirect Registers Description (Continued) Addr. 19 Power Alarm Threshold for Transistors Q1 and Q2. 20 Power Alarm Threshold for Transistors Q3 and Q4. 21 Power Alarm Threshold for Transistors Q5 and Q6. 22 Loop Closure Filter Coefficient. 23 Ring Trip Filter Coefficient. 24 Thermal Low Pass Filter Pole for Transistors Q1 and Q2. ...
Page 109
... When FSKEN = 1 and REL = 1, this register defines a gain correction factor that is applied to signal amplitude when transitioning from a mark ( space (0). D10 FSK0X[15:0] FSK0[15:0] FSK1X[15:0] FSK1[15:0] FSK01[15:0] FSK10[15:0] Description Rev. 1.0 Si3216 Reference Page 39 and AN32 39 and AN32 39 and AN32 39 and AN32 39 and AN32 39 and AN32 109 ...
Page 110
... Si3216 5. Pin Descriptions: Si3216 QFN DTX FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC Pin # Pin # Name QFN TSSOP Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high-impedance. When active, the serial port is operational. ...
Page 111
... Positive connection for transconductance gain setting resistor IRINGN Negative Ring Current Control. Analog current output driving Q3 IRINGP Positive Ring Current Control. Analog current output driving Q2 VDDA2 Analog Supply Voltage. Analog power supply for internal analog circuitry. Description Rev. 1.0 Si3216 111 ...
Page 112
... Si3216 Pin # Pin # Name QFN TSSOP 24 28 ITIPP Positive TIP Current Control. Analog current output driving Q1 ITIPN Negative TIP Current Control. Analog current output driving Q4 VDDD Digital Supply Voltage. Digital power supply for internal digital circuitry GNDD Digital Ground. Ground connection for internal digital circuitry. ...
Page 113
... Positive RING Current Drive —Connect to the IRINGP lead of the Si321x. Negative TIP Current Control —Connect to the ITIPN lead of the Si321x. Positive TIP Current Control —Connect to the ITIPP lead of the Si321x. Exposed Thermal Pad —Connect to the bulk ground plane. Rev. 1.0 Si3216 113 ...
Page 114
... Ordering Guides Device Description Wideband Codec Si3216-C-FM ProSLIC Si3216-C-GM ProSLIC Si3216M-C-FM ProSLIC Si3216M-C-GM ProSLIC Si3216-KT ProSLIC Si3216-BT ProSLIC Si3216-FT ProSLIC Si3216-GT ProSLIC Si3216M-KT ProSLIC Si3216M-BT ProSLIC Si3216M-FT ProSLIC Si3216M-GT ProSLIC Si3201-KS Linefeed Interface Si3201-BS Linefeed Interface Si3201-FS Linefeed Interface Si3201-GS Linefeed Interface Note: Add an “ ...
Page 115
... Si3216DCQX-EVB Si3216-QFN Si3216DCQ1-EVB Si3216-QFN Si3216MPPQX-EVB Si3216M-QFN Si3216MPPQ1-EVB Si3216M-QFN Si3216MDCQ1-EVB Si3216M-QFN Si3216MDCQX-EVB Si3216M-QFN Si3216PPTX-EVB Si3216-TSSOP Si3216PPT1-EVB Si3216-TSSOP Si3216DCX-EVB Si3216-TSSOP Si3216DC1-EVB Si3216-TSSOP Description Eval Board, Daughter Card Eval Board, Daughter Card Daughter Card Only Daughter Card Only Eval Board, Daughter Card Eval Board, Daughter Card ...
Page 116
... Si3216 8. Package Outline: 38-Pin QFN Figure 30 illustrates the package details for the Si321x. Table 46 lists the values for the dimensions shown in the illustration. Figure 30. 38-Pin Quad Flat No-Lead Package (QFN) Table 46. Package Diagram Dimensions Symbol aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted ...
Page 117
... D 9.60 9.70 9.80 e 0.50 BSC E 6.40 BSC E1 4.30 4.40 4.50 L 0.45 0.60 0.75 0° — 8° aaa 0.10 bbb 0.08 ccc 0.05 ddd 0.20 Rev. 1.0 Si3216 Approximate device weight is 115.7 mg 117 ...
Page 118
... Si3216 10. Package Outline: 16-Pin ESOIC Figure 32 illustrates the package details for the Si3201. Table 48 lists the values for the dimensions shown in the illustration . –A– Seating Plane Figure 32. 16-Pin Thermal Enhanced Small Outline Integrated Circuit (ESOIC) Package Table 48. Package Diagram Dimensions ...
Page 119
... Silicon Labs Si3216 Support Documentation AN32: Si321x Frequency Shift Keying (FSK) Modulation AN33: Si321x Neon Flashing AN34: Si321x Hardware Reference Guide AN35: Si321x User’s Quick Reference Guide AN39: Connecting the ProSLIC to the W & G PCM-4 ...
Page 120
... Si3216 OCUMENT HANGE IST Revision 0.61 to Revision 0.9 Separated the Si3216/15 document into two data sheets. Added Quad Flat No-Lead (QFN) package. Removed references to Si3215. Updated Figure 11 on page 20. Changed C18, C19 from 1.0 µF to 4.7 µF. ...
Page 121
... N : OTES Rev. 1.0 Si3216 121 ...
Page 122
... Si3216 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...