DS2153Q-A7+T&R Maxim Integrated Products, DS2153Q-A7+T&R Datasheet - Page 19

IC TXRX E1 1-CHIP 5V 44-PLCC

DS2153Q-A7+T&R

Manufacturer Part Number
DS2153Q-A7+T&R
Description
IC TXRX E1 1-CHIP 5V 44-PLCC
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS2153Q-A7+T&R

Function
Single-Chip Transceiver
Interface
E1
Number Of Circuits
1
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
65mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Power (watts)
-
RIR: RECEIVE INFORMATION REGISTER (Address = 08 Hex)
(MSB)
TESF
SYMBOL
CRCRC
CASRC
FASRC
RESE
TESF
TESE
JALT
RESF
TESE
POSITION
RIR.7
RIR.6
RIR.5
RIR.4
RIR.3
RIR.2
RIR.1
RIR.0
JALT
NAME AND DESCRIPTION
Transmit Elastic Store Full. Set when the elastic store fills and
a frame is deleted.
Transmit Elastic Store Empty. Set when the elastic store
empties and a frame is repeated.
Jitter Attenuator Limit Trip. Set when the jitter attenuator
FIFO reaches to within 4 bits of its limit; useful for debugging
jitter attenuation operation.
Elastic Store Full. Set when the elastic store buffer fills and a
frame is deleted.
Elastic Store Empty. Set when the elastic store buffer empties
and a frame is repeated.
CRC Resync Criteria Met. Set when 915/1000 codewords are
received in error.
FAS Resync Criteria Met. Set when three consecutive FAS
words are received in error.
CAS Resync Criteria Met. Set when two consecutive CAS MF
alignment words are received in error.
RESF
19 of 60
RESE
CRCRC
FASRC
CASRC
(LSB)

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