SI3215-FT Silicon Laboratories Inc, SI3215-FT Datasheet
SI3215-FT
Specifications of SI3215-FT
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SI3215-FT Summary of contents
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... CMOS integrated circuit. The integrated battery supply continuously adapts its output voltage to minimize power and enables the entire solution to be powered from a single 3.3 V (Si3215M only supply. The ProSLIC controls the phone line through Silicon Labs’ Si3201 Linefeed Interface Chip or discrete component line feed ...
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... Si3215 2 Rev. 0.92 ...
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... Section 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.1. Si3210 to Si3215 Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.2. Linefeed Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.3. Battery Voltage Generation and Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2.4. Tone Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2.5. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6. Audio Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.7. Two-Wire Impedance Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.8. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 2.9. Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.10. Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2 ...
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... Exposure to absolute maximum rating conditions for extended periods may affect device reliability Operation above 125 C junction temperature may degrade device reliability. 3. Thermal resistance assumes a multi-layer PCB with the exposed pad soldered to a topside PCB pad Symbol Si3215 DDD DDA1 DDA2 I IN ...
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... Table 2. Recommended Operating Conditions Parameter Ambient Temperature Ambient Temperature Si3215 Supply Voltage Si3201 Supply Voltage Si3201 Battery Voltage *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 Product specifications are only guaranteed when the typical application circuit (including component tolerances) is used ...
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... Si3215 Table 3. AC Characteristics (Continued 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter 2-Wire Return Loss Transhybrid Balance 4 Idle Channel Noise PSRR from VDDA PSRR from VDDD PSRR from VBAT Longitudinal to Metallic or PCM Balance Metallic to Longitudinal Balance ...
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... Figure 1. Transmit and Receive Path SNDR Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Rev. 0.92 Si3215 Acceptable Region ...
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... Si3215 Figure 3. Transmit Path Frequency Response 8 Typical Response Typical Response Rev. 0.92 ...
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... Figure 4. Receive Path Frequency Response Rev. 0.92 Si3215 9 ...
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... Si3215 Figure 5. Transmit Group Delay Distortion 10 Figure 6. Receive Group Delay Distortion Rev. 0.92 ...
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... Indirect Register 23 5 REN load; sine wave 160 Ω –75 V LOOP BAT Programmable in Indirect OS Register 6 Crest factor = 1 Accuracy of ON/OFF Times ↑CAL to ↓CAL Bit At Power Threshold = 300 mW Rev. 0.92 Si3215 Min Typ Max Unit Ω 0 — 160 –10 — –4 — Ω ...
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... Si3215 Table 5. Monitor ADC Characteristics ( 3. °C for K-Grade, – °C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit resolution) Integral Nonlinearity INLE (6-bit resolution) Gain Error (voltage) Gain Error (current) Table 6. Si321x DC Characteristics 4. °C for K-Grade, – °C for B-Grade) ...
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... BAT I Sleep (RESET = 0) BAT Open (DCOF = 1) Active on-hook ETBO = Active OHT ETBO = 4 mA Active off-hook ETBA = 4 mA LIM Ground-start Ringing PK_RING PK sinewave ringing, REN = 1 When using Si3201 x V BAT BAT Rev. 0.92 Si3215 1 2 Max Typ Typ 0.1 0.13 0 — ...
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... Si3215 Table 9. Switching Characteristics—General Inputs 3. °C for K-Grade, – °C for B-Grade, C DDA DDA A Parameter Rise Time, RESET RESET Pulse Width Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are V ...
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... Figure 7. SPI Timing Diagram = Test Symbol Conditions 1 dty t jitter su1 su2 t h2 Rev. 0.92 Si3215 Units Min Typ Max — 0.256 — MHz — 0.512 — MHz — 0.768 — MHz — 1.024 — MHz — 1.536 — MHz — ...
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... O nly on e com pone system nee ded . circuit gro und shou ld h ave a sing le -po int 1 5 conn ection to the gro und plan 201 botto m -sid e exposed pa d sho uld be electrica lly erm a lly con nected gro und pla ne . Figure 9. Si3215/Si3215M Application Circuit Using Si3201 ...
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... Values and configurations for these components can be derived from Table 21 or from “AN45: Design Guide for the Si3210 DC-DC Converter”. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 10. Si3215 BJT/Inductor DC-DC Converter Circuit Value 220 nF, 100 V, X7R, ±20% 22 nF, 100 V, X7R, ±20% 0.1 µ ...
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... Si3215 Table 13. Si3215 BJT/Inductor DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% C10 0.1 µ X7R, ±20% 1 C14 1 C25 10 µF, Electrolytic, ±20% R16 R17 1/10 W, ±5% (See AN45 R18 1/4 W, ±5% (See AN45 or Table 19 for value selection) R19,R20 1/10 W, ±1% (See AN45 or Table 19 for value selection) ...
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... Table 20 or from “AN45: Design Guide for the Si3210 DC-DC Converter”. 2. Voltage rating for C14 and C25 must be greater than VDC. Figure 11. Si3215M MOSFET/Transformer DC-DC Converter Circuit Table 14. Si3215M MOSFET/Transformer DC-DC Converter Component Values Component( µF, 100 V, Electrolytic, ±20% ...
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... Only one component per system needed. 3. All circuit grounds should have a single-point connection to the ground plane. 4. Optional components to improve idle channel noise Figure 12. Si3215/Si3215M Typical Application Circuit Using Discrete Components Table 15. Si3215/Si3215M External Component Values—Discrete Solution Component C1,C2 10 µ Ceramic Low Leakage Electrolytic, 220 nF, 100 V, X7R, ± ...
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... Table 15. Si3215/Si3215M External Component Values—Discrete Solution (Continued) Q9 NPN General Purpose BJT R1,R3 R2,R4,R5, R102,R104, R105 R6,R7 R8,R9 R10,R11 R12,R13 40.2 k Ω , 1/10 W, ± 1% R14,R26* R15 R21 1/10 W, ± 1% (See AN45 or Table 17 for value selection) R28,R29 R32* Note: Only one component per system needed. ...
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... Note: There are other system and software conditions that influence component value selection. Please refer to “AN45: Design Guide for the Si3210 DC-DC Converter” for detailed information. Table 19. Component Value Selection Examples for Si3215 BJT/Inductor DC-DC Converter VDC Maximum Ringing Load/Loop Resistance 3 REN/117 Ω ...
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... SPI. The device is available in 38-pin QFN or TSSOP packages. 2.1. Si3210 to Si3215 Differences The Si3215 is very similar to the Si3210 in terms of its operation. The complete functionality of the Si3215 is covered in this data sheet. There are some hardware and software differences between the Si3215 and the ...
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... Si3215 2.2.1. DC Feed Characteristics The ProSLIC has programmable constant voltage and constant current zones as depicted in Figure 14. Open circuit TIP-to-RING voltage (V ) defines the constant OC voltage zone and is programmable from 94 1.5 V steps. The loop current limit (I constant current zone and is programmable from steps. The ProSLIC has an inherent ) of 160 Ω ...
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... In RING open and TIP open states, the loop current is reported – Monitor A/D A/D DSP D/A SLIC DAC Σ DC Sense Si3201 Control Loop Rev. 0.92 Si3215 – reported TIP RING + I –I )/2, is reported – Battery Sense DC Emitter Sense Control BAT V BAT 25 ...
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... Si3215 Table 21. ProSLIC Linefeed Operations LF[2:0]* Linefeed State 000 Open 001 Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open *Note: The Linefeed register (LF) is located in direct Register 64. ...
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... Q6, respectively 0 to 7.8 W for Q1, 30.4 mW Q2, Q5 0.9 W for Q3 7 0 7.8 W 30.4 mW See equation above. See equation above. See equation above. Bits corre- N/A spond Q6, respectively Rev. 0.92 Si3215 4096 3 × ------------------ 2 = 800 τ × 1. × ----------------- - × 5389 = 150D 0 ...
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... Si3215 Table 23. Associated Power Monitoring and Power Fault Registers (Continued) Power Alarm Interrupt Enable Power Alarm Automatic/Manual Detect *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A direct register is one that is mapped directly. An indirect register is one that is accessed using the indirect access registers (direct registers 28 through 31) ...
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... It is recommended that a calibration be executed following system power-up. Upon release of the chip reset, the Si3215 will be in the open state. After powering up the dc-dc converter and allowing it to settle for time (t ) the calibration can be initiated. ...
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... DCFF and DCDRV together is not recommended. 2.3.4. DC-DC Converter Architecture The control logic for a pulse width modulated (PWM) dc- dc converter is incorporated in the Si3215. Output pins, DCDRV and DCFF, are used to switch a bipolar transistor or MOSFET. The polarity of DCFF is opposite that of DCDRV. ...
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... The power LOOP hook terminal LIM TIP RING and V in the Forward Active State TIP RING BAT Rev. 0.92 Si3215 the brief on-hook Constant V Region R V TIP | voltage LOOP RING BAT 31 ...
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... An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). 2.3.5. DC-DC Converter Enhancements The Si3215 supports two enhancements to the dc-dc converter. The first is a multi-threshold error control algorithm that enables the dc-dc converter to adjust more quickly to voltage changes. This option is enabled by setting DCSU = 1 (direct Register 108, bit 5) ...
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... O1E (direct Register 32, bit 2). The 16-bit counter will × 0.5 692 2B3h = = begin counting until the active timer expires, at which time the 16-bit counter will reset to zero and begin Rev. 0.92 Si3215 to TX Path Signal Routing to RX Path OnSO 2π1336 ⎛ ⎞ ------------------- - ...
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... Si3215 counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature can be implemented by setting the OZ1 bit (direct Register 32, bit 5). This ensures that each oscillator pulse ends without a dc component ...
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... Table 28 summarizes the list of registers used for ringing generation. Note: Tone generator 2 should not be enabled concurrently with the ringing generator due to resource sharing within the hardware. Rev. 0.92 Si3215 ... ... ... , O AT1 0,1 ... ...
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... Si3215 Table 28. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control (Initiates Ringing State) High Battery Voltage Ringing dc voltage offset ...
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... V = amplitude of the ac ringing waveform. AC,PK = 200 = C8h It is good practice to provide a buffer of a few more milliamperes for I leakages, etc. The total I = 5EABh smaller than 80 mA. Rev. 0.92 Si3215 ( ) × 2 24235 ------------------------------------- - = = 396 = 018Ch × 0.0153 8000 , is added to the ringing signal when ...
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... Si3215 β × × ( 80.6 Ω ------------ - OVR LOAD,PK β where β is the minimum expected current gain of transistors Q5 and Q6. The minimum value for V is, therefore, given by the BATH following: VBATH = AC,PK ROFF The ProSLIC is designed to create a fully balanced ringing waveform, meaning that the TIP and RING ...
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... PCM_Mode register selection, every 8-bit compressed serial data word will occupy one time slot on the PCM highway, or every 16-bit uncompressed serial data word will occupy two time slots on the PCM highway. Rev. 0.92 Si3215 Location Direct Register 19 Direct Register 22 Direct Register 70 ...
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... Si3215 40 Rev. 0.92 ...
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... Figure 22.) The signal path starts with the analog signal at the input of the transmit path and ends with an analog signal at the output of Rev. 0.92 Si3215 , while the transmit path 41 ...
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... The default setting of CLC[2:0] assumes no line capacitance. The Si3215 supports the option to remove the internal reference resistor used to synthesize ac impedances for 600 + 1 µF and 900 + 2.16 µF settings so that an external resistor reference may be used ...
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... Each device uses the LSB of the chip select byte, shifts the data right by one bit, and passes the chip select byte using the SDITHRU pin to the next device in the chain. Address/control and data bytes are unaltered. Rev. 0.92 Si3215 43 ...
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... Si3215 SCLK CS SDI SDO SCLK CS SDI SDO High Impedance 44 Don't Care High Impedance Figure 24. Serial Write 8-Bit Mode Don't Care Figure 25. Serial Read 8-Bit Mode Rev. 0. Don't Care ...
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... Note: During chip select byte, SDITHRU = SDI delayed by one SCLK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. CS SDO SDITHRU CS SDO SDITHRU CS SDO SDITHRU CS SDO SDITHRU Address Byte R/W Figure 26. SPI Daisy Chain Mode Rev. 0.92 Si3215 SDI0 SDI SDI1 SDI SDI2 SDI SDI3 SDI Data Byte ...
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... Si3215 2.11. PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM Mode Select (direct Register 1), PCM Transmit Start Count (direct registers 2 and 3), and PCM Receive Start Count (direct registers 4 and 5) registers ...
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... Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected via the PCMF register. Tables 31 and 32 define the µ-Law and A-Law encoding formats MSB MSB LSB Rev. 0.92 Si3215 LSB HI-Z LSB HI-Z 47 ...
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... Si3215 Table 31. µ-Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 __________________ Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative analog values. 2. Digital code includes inversion of all magnitude bits. 48 Value at Segment Endpoints Digital Code 8159 10000000b ...
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... Digital code includes inversion of all even numbered bits. Value at segment endpoints Digital Code 4096 3968 10101010b . . 2176 2048 10100101b . . . 1088 1024 10110101b . . . 544 512 10000101b . . . 272 256 10010101b . . . 136 128 11100101b . . . 68 64 11110101b . . . 2 0 11010101b Rev. 0.92 Si3215 1,2 Decode Level 4032 2112 1056 528 264 132 ...
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... Si3215 3. Control Registers Note: Any register not listed here is reserved and must not be written. Register Name 0 SPI Mode Select 1 PCM Mode Select 2 PCM Transmit Start Count—Low Byte 3 PCM Transmit Start Count—High Byte 4 PCM Receive Start Count—Low Byte 5 PCM Receive Start Count— ...
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... OIT1[15:8] OAT2[7:0] OAT2[15:8] OIT2[7:0] OIT2[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH CBY ETBE VOV MNCM MNDIF SPDS Rev. 0.92 Si3215 Bit 3 Bit 2 Bit 1 Bit 0 IAS O1TIE O1E O1SO[1:0] O2TIE O2E O2SO[1:0] RTIE ROE RVO TSWS FSKDAT LF[2:0] ETBO[1:0] ETBA[1:0] ...
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... Si3215 Table 33. Direct Register Summary (Continued) Register Name 68 Loop Closure/Ring Trip Detect Status 69 Loop Closure Debounce Interval 70 Ring Trip Detect Debounce Interval 71 Loop Current Limit 72 On-Hook Line Voltage 73 Common Mode Voltage 74 High Battery Voltage 75 Low Battery Voltage 76 Power Monitor Pointer 77 Line Power Output ...
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... DC Peak Current Monitor Calibration Result 108 Enhancement Enable Bit 7 Bit 6 Bit 5 Bit 4 CAL CALSP CALR CALM1 CALMG1[3:0] DACOF[7:0] ILIMEN FSKEN DCSU Rev. 0.92 Si3215 Bit 3 Bit 2 Bit 1 Bit 0 CALT CALD CALC CALIL CALM2 CALDAC CALADC CALCM CALGMR[4:0] CALGMT[4:0] CALGD[4:0] CALGC[4:0] CALGIL[3:0] ...
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... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3215 01 = Unused 10 = Unused 11 = Si3215M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc PNI[1:0] R Function Rev ...
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... Bit D7 D6 Name PNI2 PCME Type R Reset settings = 1000_1000 Bit Name 7 PNI2 Part Number Identification Si3210 family 1 = Si3215 family 6 Reserved Read returns zero. 5 PCME PCM Enable Disable PCM transfers Enable PCM transfers. 4:3 PCMF[1:0] PCM Format A-Law 01 = µ-Law 10 = Reserved 11 = Linear ...
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... Si3215 Register 3. PCM Transmit Start Count—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 TXS[9:8] PCM Transmit Start Count. PCM transmit start count equals the number of PCLKs following FSYNC before data transmission begins. See Figure 27 on page 46. ...
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... Type R Reset settings = 0xx0_0000 Bit Name 7:5 PNI[2:0] Part Number Identification. Note: PNI[2] can be read in direct Register 1. PNI[1:0] can be read in direct Register 0. 000 = Si3215 001 = Reserved 010 = Reserved 011 = Si3215M 4:0 Reserved Read returns zero. Register 8. Audio Path Loopback Control Bit ...
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... Si3215 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive path, RHDF HPF bypassed in receive path, RHDF. 6 TXHP Transmit Path High Pass Filter Disable. ...
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... Australia/New Zealand 220 Ω + (820 Ω || 120 nF) 110 = Slovakia/Slovenia/South Africa 220 Ω + (820 Ω || 115 nF) 111 = China 200 Ω + (680 Ω || 100 nF CLC[1:0] TISE R/W R/W Function Rev. 0.92 Si3215 TISS[2:0] R Ω and C3 100 nF. ZREF = 18 k Ω and C3 220 nF. ZREF 59 ...
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... Si3215 Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 dB 010 = 1.16 dB 011 = 0 dB 100 = –1.02 dB 101 = –1.94 dB 110 = –2.77 dB 111 = Off 3 Reserved Read returns zero ...
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... DC Bias Power-Off Control Automatic power control Override automatic control and force dc bias circuitry off. 0 SLICOF SLIC Power-Off Control Automatic power control Override automatic control and force SLIC circuitry off DCOF PFR R/W R/W Function Rev. 0.92 Si3215 BIASOF SLICOF R/W R/W 61 ...
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... Si3215 Register 15. Powerdown Control 2 Bit D7 D6 Name ADCM Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control Automatic power control Manual power control; ADCON controls on/off state. 4 ADCON Analog to Digital Converter On/Off Power Control. ...
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... Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 O1AP Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending RGAP O2IP O2AP R/W R/W R/W Function Rev. 0.92 Si3215 O1IP O1AP R/W R/W R/W 63 ...
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... Si3215 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 6 Q5AP Power Alarm Q5 Interrupt Pending. Writing 1 to this bit clears a pending interrupt. ...
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... Read returns zero. 1 INDP Indirect Register Access Serviced Interrupt. This bit is set once a pending indirect register service request has been completed. Writ- ing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 Reserved Read returns zero Function Rev. 0.92 Si3215 INDP R/W 65 ...
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... Si3215 Register 21. Interrupt Enable 1 Bit D7 D6 Name RGIE Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 RGIE Ringing Inactive Timer Interrupt Enable Interrupt masked Interrupt enabled. 4 RGAE Ringing Active Timer Interrupt Enable Interrupt masked Interrupt enabled. 3 O2IE Oscillator 2 Inactive Timer Interrupt Enable. ...
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... Power Alarm Q1 Interrupt Enable Interrupt masked Interrupt enabled. 1 LCIE Loop Closure Transition Interrupt Enable Interrupt masked Interrupt enabled. 0 RTIE Ring Trip Interrupt Enable Interrupt masked Interrupt enabled Q3AE Q2AE Q1AE R/W R/W R/W Function Rev. 0.92 Si3215 LCIE RTIE R/W R/W R/W 67 ...
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... Si3215 Register 23. Interrupt Enable 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 Reserved Read returns zero Function Rev. 0. INDE R/W ...
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... IAA at the next indirect register update (16 kHz update rate—a write operation). Writing IAA only will load IDA with the value stored at IAA at the next indirect memory update (a read operation IDA[7:0] R/W Function IDA[15:8] R/W Function Rev. 0.92 Si3215 ...
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... Si3215 Register 30. Indirect Address Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IAA[7:0] Indirect Address Access. A write to IDA followed by a write to IAA will place the contents of IDA into an indirect register at the location referenced by IAA at the next indirect register update (16 kHz update rate— ...
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... O1E Oscillator 1 Enable Disable oscillator Enable oscillator. 1:0 O1SO[1:0] Oscillator 1 Signal Output Routing Unassigned path (output not connected Assign to transmit path Assign to receive path Assign to both paths OZ1 O1TAE O1TIE R/W R/W R/W Function Rev. 0.92 Si3215 O1E O1SO[1:0] R/W R/W 71 ...
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... Si3215 Register 33. Oscillator 2 Control Bit D7 D6 Name OSS2 Type R Reset settings = 0000_0000 Bit Name 7 OSS2 Oscillator 2 Signal Status Output signal inactive Output signal active. 6 Reserved Read returns zero. 5 OZ2 Oscillator 2 Zero Cross Enable Signal terminates after active timer expires Signal terminates at zero crossing. ...
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... ROE Ringing Oscillator Enable Ringing oscillator disabled Ringing oscillator enabled. 1 RVO Ringing Voltage Offset offset added to ringing signal offset added to ringing signal. 0 TSWS Trapezoid/Sinusoid Waveshape Select Sinusoid 1 = Trapezoid RTAE RTIE ROE R R/W R/W Function Rev. 0.92 Si3215 RVO TSWS R R/W R/W 73 ...
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... Si3215 Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 µs Register 37. Oscillator 1 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[15:8] Oscillator 1 Active Timer. Register 38. Oscillator 1 Inactive Timer— ...
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... Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 µs Register 41. Oscillator 2 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[15:8] Oscillator 2 Active Timer OIT1[15:8] R/W Function OAT2[7:0] R/W Function OAT2[15:8] R/W Function Rev. 0.92 Si3215 ...
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... Si3215 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 µs Register 43. Oscillator 2 Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[15:8] Oscillator 2 Inactive Timer. Register 48. Ringing Oscillator Active Timer— ...
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... RIT[7:0] Ringing Inactive Timer. LSB = 125 µs Register 51. Ringing Oscillator Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RIT[15:8] Ringing Inactive Timer RAT[15:8] R/W Function RIT[7:0] R/W Function RIT[15:8] R/W Function Rev. 0.92 Si3215 ...
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... Si3215 Register 52. FSK Data Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 FSKDAT FSK Data. When FSKEN = 1 (direct Register 108, bit 6) and REL = 1 (direct Register 32, bit 6), this bit serves as the buffered input for FSK generation bit stream data. ...
Page 79
... Read returns zero. 2:0 LF[2:0] Linefeed. Writing to this register sets the linefeed state. 000 = Open 001 = Forward active 010 = Forward on-hook transmission 011 = TIP open 100 = Ringing 101 = Reverse active 110 = Reverse on-hook transmission 111 = RING open Function Rev. 0.92 Si3215 LF[2:0] R/W 79 ...
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... Si3215 Register 65. External Bipolar Transistor Control Bit D7 D6 Name SQH Type R/W Reset settings = 0110_0001 Bit Name 7 Reserved Read returns zero. 6 SQH Audio Squelch squelch STIPAC and SRINGAC pins squelched. 5 CBY Capacitor Bypass Capacitors CP (C1) and CM (C2) in circuit Capacitors CP (C1) and CM (C2) bypassed. ...
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... BAT 0 = Normal operation tracks V BAT 2:1 Reserved Read returns zero. 0 TRACK DC-DC Converter Tracking Mode will not decrease below V BAT tracks V BAT VOV FVBAT R/W R/W Function OV register. BATH . BATL . RING Rev. 0.92 Si3215 TRACK R/W , which is defined in indirect Register 64. 81 ...
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... Si3215 Register 67. Automatic/Manual Control Bit D7 D6 Name MNCM MNDIF Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 MNCM Common Mode Manual/Automatic Select Automatic control Manual control, in which TIP (forward) or RING (reverse) forces voltage to follow VCM value. 5 MNDIF Differential Mode Manual/Automatic Select. ...
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... LCDI[6:0] Loop Closure Debounce Interval. The value written to this register defines the minimum steady state debounce time. Value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12.5 ms DBIRAW Function LCDI[6:0] R/W Function Rev. 0.92 Si3215 RTP LCR ...
Page 84
... Si3215 Register 70. Ring Trip Detect Debounce Interval Bit D7 D6 Name Type Reset settings = 0000_1010 Bit Name 7 Reserved Read returns zero. 6:0 RTDI[6:0] Ring Trip Detect Debounce Interval. The value written to this register defines the minimum steady state debounce time. The value may be set between 0 ms (0x00) to 159 ms (0x7F) in 1.25 ms steps. Default value = 12 ...
Page 85
... The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = – VOC[5:0] R/W Function is positive RING is negative RING VCM[5:0] R/W Function for forward active and forward on-hook trans- TIP for reverse active and reverse on-hook transmission states. RING Rev. 0.92 Si3215 –V ). TIP RING –V ). Value may TIP RING ...
Page 86
... Si3215 Register 74. High Battery Voltage Bit D7 D6 Name Type Reset settings = 0011_0010 Bit Name 7:6 Reserved Read returns zero. 5:0 VBATH[5:0] High Battery Voltage. The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = – ...
Page 87
... Line Power Output Monitor. This register reports the real time power output of the transistor selected using PWRMP. The range (0x00) to 7.8 W (0xFF) in 30.4 mW steps for Q1, Q2, Q5, and Q6. The range (0x00) to 0.9 W (0xFF) in 3.62 mW steps for Q3 and Q4 Function PWROM[7:0] R Function Rev. 0.92 Si3215 PWRMP[2:0] R ...
Page 88
... Si3215 Register 78. Loop Voltage Sense Bit D7 D6 Name LVSP Type R Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 LVSP Loop Voltage Sense Polarity. This register reports the polarity of the differential loop voltage ( Positive loop voltage ( Negative loop voltage (V 5:0 LVS[5:0] Loop Voltage Sense Magnitude ...
Page 89
... Reset settings = 0000_0000 Bit Name 7:0 VBATS1[7:0] Battery Voltage Sense 1. This register is one of two registers that reports the real time voltage ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps VTIP[7:0] R Function VRING[7:0] R Function VBATS1[7:0] R Function Rev. 0.92 Si3215 with respect BAT 89 ...
Page 90
... Si3215 Register 83. Battery Voltage Sense 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VBATS2[7:0] Battery Voltage Sense 2. This register is one of two registers that reports the real time voltage ground. The range (0x00) to –95.88 V (0xFF) in .376 V steps. Register 84. Transistor 1 Current Sense ...
Page 91
... Register 88. Transistor 5 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ5[7:0] Transistor 5 Current Sense. This register reports the real time current through Q5. The range (0x00) to 80.58 mA (0xFF) in .316 mA steps IQ3[7:0] R Function IQ4[7:0] R Function IQ5[7:0] R Function Rev. 0.92 Si3215 ...
Page 92
... Si3215 Register 89. Transistor 6 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ6[7:0] Transistor 6 Current Sense. This register reports the real time current through Q6. The range (0x00) to 80.58 mA (0xFF) in .316 mA steps. Register 92. DC-DC Converter PWM Period Bit D7 D6 ...
Page 93
... DC-DC Converter Feed Forward Pin (DCFF) Polarity. This read-only register bit indicates the polarity relationship of the DCFF pin to the DCDRV pin. Two versions of the Si3215 are offered to support the two relationships DCFF pin polarity is opposite of DCDRV pin (Si3215 DCFF pin polarity is same as DCDRV pin (Si3215M). ...
Page 94
... Si3215 Register 94. DC-DC Converter PWM Pulse Width Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width. Pulse width of DCDRV is given (DCPW – DCTOF – 61.035 ns DCPW[7:0] R Function Rev. 0. ...
Page 95
... Common Mode DAC Gain Calibration Normal operation or calibration complete Calibration enabled or in progress. 0 CALIL I Calibration. LIM 0 = Normal operation or calibration complete Calibration enabled or in progress CALR CALT CALD R/W R/W R/W Function Rev. 0.92 Si3215 CALC CALIL R/W R/W R/W settling at the beginning of the BAT 95 ...
Page 96
... Si3215 Register 97. Calibration Control/Status Register 2 Bit D7 D6 Name Type Reset settings = 0001_1111 Bit Name 7:5 Reserved Read returns zero. 4 CALM1 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or in progress. 3 CALM2 Monitor ADC Calibration Normal operation or calibration complete Calibration enabled or in progress. ...
Page 97
... Register 100. Differential Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGD[4:0] Differential DAC Gain Calibration Result CALGMR[4:0] R/W Function CALGMT[4:0] R/W Function CALGD[4:0] R/W Function Rev. 0.92 Si3215 ...
Page 98
... Si3215 Register 101. Common Mode Loop Current Gain Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0001 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGC[4:0] Common Mode DAC Gain Calibration Result. Register 102. Current Limit Calibration Result Bit D7 D6 Name ...
Page 99
... Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result DACP DACN R/W R/W Function DACOF[7:0] R/W Function Function Rev. 0.92 Si3215 ADCP ADCN R/W R CMDCPK[3:0] R/W 99 ...
Page 100
... Si3215 Register 108. Enhancement Enable Bit D7 D6 Name ILIMEN FSKEN DCSU Type R/W R/W Reset settings = 0000_0000 Bit Name 7 ILIMEN Current Limit Increase. When enabled, this bit temporarily increases the maximum differential current limit at the end of a ring burst to enable a faster settling time linefeed state. ...
Page 101
... IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of 16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer. Table 34. Si3210 to Si3215 Indirect Register Cross Reference Si3210 Si3215 ...
Page 102
... Si3215 4.1. Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes ...
Page 103
... This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to – ∞ dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Description D11 D10 DACG[11:0] ADCG[11:0] Description Rev. 0.92 Si3215 Reference Page Reference Page 39 39 ...
Page 104
... Si3215 4.3. SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. Shaded areas denote bits that can be read and written but should be written to zeroes ...
Page 105
... Register 32, bit 6). Table 41. FSK Control Indirect Registers Summary Addr. D15 D14 D13 D12 Description , to be supplied by the dc-dc converter. OV should be set between 0 and should be set between 0 and 13 D11 D10 FSK0X[15:0] FSK0[15:0] FSK1X[15:0] FSK1[15:0] FSK01[15:0] FSK10[15:0] Rev. 0.92 Si3215 Reference Page 105 ...
Page 106
... Si3215 Table 42. FSK Control Indirect Registers Description Addr 69 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a space or “0”. When the active timer (OAT1) expires, the value of this register is loaded into oscillator 1 instead of OSC1X. ...
Page 107
... Pin Descriptions: Si3215 DTX FSYNC 2 RESET 3 SDCH 4 SDCL DDA1 IREF 7 CAPP 8 QGND 9 CAPM 10 STIPDC 11 SRINGDC Pin # Pin # Name QFN TSSOP Chip Select. Active low. When inactive, SCLK and SDI are ignored and SDO is high impedance. When active, the serial port is operational. ...
Page 108
... Si3215 Pin # Pin # Name QFN TSSOP 5 9 SDCL DC Monitor. DC-DC converter monitor input used to detect overcurrent situations in the con- verter Analog Supply Voltage. DDA1 Analog power supply for internal analog circuitry IREF Current Reference. Connects to an external resistor used to provide a high accuracy reference current. ...
Page 109
... Serial Port Data Out. Serial port control data output SDI Serial Port Data In. Serial port control data input SCLK Serial Port Bit Clock Input. Serial port clock input. Controls the serial data on SDO and latches the data on SDI. Description Rev. 0.92 Si3215 109 ...
Page 110
... Si3215 6. Pin Descriptions: Si3201 Pin # Name Input/ Output 1 TIP I — 3 RING I/O 4 VBAT — 5 VBATH — 7 GND — 8 VDD — 10 SRINGE O 11 STIPE O 13 IRINGN I 14 IRINGP I 15 ITIPN I 16 ITIPP I Bottom-Side — Exposed Pad 110 TIP 1 16 ITIPP ITIPN RING ...
Page 111
... Ordering Guide Device Description Si3215-X-FM ProSLIC Si3215-X-GM ProSLIC Si3215M-X-FM ProSLIC Si3215M-X-GM ProSLIC Si3215-FT ProSLIC Si3215-GT ProSLIC Si3215M-FT ProSLIC Si3215M-GT ProSLIC Si3215-KT ProSLIC Si3215-BT ProSLIC Si3215M-KT ProSLIC Si3215M-BT ProSLIC Si3201-FS Line Interface Si3201-GS Line Interface Si3201-KS Line Interface Si3201-BS Line Interface Notes: 1. “ ...
Page 112
... Supported Description ProSLIC Si3215-QFN Evaluation Board, Daughter Card Si3215-QFN Evaluation Board, Daughter Card Si3215-QFN Daughter Card Only Si3215-QFN Daughter Card Only Si3215M-QFN Evaluation Board, Daughter Card Si3215M-QFN Evaluation Board, Daughter Card Si3215M-QFN Daughter Card Only Si3215M-QFN Daughter Card Only Rev. 0.92 ...
Page 113
... J-STD-020C specification for Small Body Components. Rev. 0.92 Si3215 Bottom Side Exposed Pad 3.2 x 5.2 mm 1,2,3 Max 0.95 0.05 0.30 3.30 5.30 0.55 0.08 0.10 0.10 0.08 ...
Page 114
... Si3215 9. Package Outline: 38-Pin TSSOP Figure 32 illustrates the package details for the Si321x. Table 45 lists the values for the dimensions shown in the illustration. E/2 2x ddd aaa C Seating Plane C Figure 32. 38-Pin Thin Shrink Small Outline Package (TSSOP) Table 45. Package Diagram Dimensions 114 ...
Page 115
... Weight: Approximate device weight is 0.15 grams. Millimeters Symbol Min Max A 1.35 1. 0.15 B .33 .51 C .19 .25 D 9.80 10.00 E 3.80 4.00 e 1.27 BSC H 5.80 6.20 h .25 .50 L .40 1.27 γ — 0.10 θ 0º 8º Rev. 0.92 Si3215 x45° h θ L Detail F C See Detail F 115 ...
Page 116
... Ordering Guide" on page 111. Updated to include product revision designator Table 43, “Evaluation Kit Ordering Guide,” on page 112. Updated to include “M” version of device. Table 15, “Si3215/Si3215M External Component Values—Discrete Solution,” on page 20. Added TO-92 transistor suppliers to BOM. Table 46, “Package Diagram Dimensions,” on page 115 Changed A1 max from 0 ...
Page 117
... N : OTES Rev. 0.92 Si3215 117 ...
Page 118
... Si3215 C I ONTACT NFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...