MAX3107EAG+ Maxim Integrated Products, MAX3107EAG+ Datasheet - Page 46

• Manufacturer Part Number: MAX3107EAG+
• Description: IC UART SPI/I2C 128 FIFO 24SSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX3107EAG+

• Features: Internal Oscillators
• Number Of Channels: 4, QUART
• Fifo's: 128 Byte
• Protocol: RS232, RS485
• Voltage - Supply: 2.35 V ~ 3.6 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• Mounting Type: Surface Mount
• Package / Case: 24-SSOP
• Data Rate: 24 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.71 V
• Supply Current: 4 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 19. Burst Write Sequence
Figure 20. Read Byte Sequence
SPI/I
and Internal Oscillator
Figure 18. Write Byte Sequence
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data
4) The master sends the 8-bit register address.
5) The slave asserts an ACK on the data line only if the
6) The master sends 8 bits of data.
7) The slave asserts an ACK on the data line.
8) Repeat steps 6 and 7 N - 1 times.
9) The master generates a STOP condition.
46
line.
address is valid (NACK if not).
_____________________________________________________________________________________
2
C UART with 128-Word FIFOs
BURST WRITE
S
READ SINGLE BYTE
WRITE SINGLE BYTE
FROM MASTER TO STAVE
Sr
S
S
FROM MASTER TO STAVE
FROM MASTER TO STAVE
DEVICE SLAVE ADDRESS - W
DEVICE SLAVE ADDRESS - W
DEVICE SLAVE ADDRESS - R
DEVICE SLAVE ADDRESS - W
8 DATA BITS - 1
8 DATA BITS
FROM SLAVE TO MASTER
FROM SLAVE TO MASTER
FROM SLAVE TO MASTER
A
A
A
A
A
A
With this operation the master sends an address and
receives 1 or 2 data bytes from the slave device
(Figure 20). The read byte procedure is as follows:
1) The master sends a START condition.
2) The master sends the 7-bit slave ID plus a write bit (low).
3) The addressed slave asserts an ACK on the data line.
4) The master sends the 8-bit register address.
5) The active slave asserts an ACK on the data line only
6) The master sends a repeated START (Sr).
REGISTER ADDRESS
if the address is valid (NACK if not).
P
8 DATA BITS - N
8 DATA BITS - 2
REGISTER ADDRESS
REGISTER ADDRESS
8 DATA BITS
A
A
A
NA
A
A
P
P
Single-Byte Read