PC16552DVX/NOPB National Semiconductor, PC16552DVX/NOPB Datasheet
PC16552DVX/NOPB
Specifications of PC16552DVX/NOPB
*PC16552DVX/NOPB
PC16552DVX
PC16552DVXTR
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PC16552DVX/NOPB Summary of contents
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... The DUART is fabricated using National Semiconductor’s 2 advanced M CMOS TM TRI-STATE is a registered trademark of National Semiconductor Corporation 2 M CMOS trademark of National Semiconductor Corporation C 1995 National Semiconductor Corporation TL C 9426 ...
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ABSOLUTE MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS 4 0 TIMING WAVEFORMS 5 0 BLOCK DIAGRAM OF A SINGLE SERIAL CHANNEL 6 0 PIN DESCRIPTIONS 6 1 Input Signals 6 2 Output Signals ...
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Absolute Maximum Ratings Temperature under Bias Storage Temperature All Input or Output Voltages with Respect Power Dissipation Electrical Characteristics ...
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AC Electrical Characteristics Symbol Parameter t RD Delay from Address Delay from Address AW t Data Hold Time DH t Data Setup Time Floating Data Delay HZ t Master Reset Pulse ...
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AC Electrical Characteristics Symbol Parameter TRANSMITTER t Delay from WR (WR THR Reset Interrupt t Delay from RD (RD IIR) to Reset IR Interrupt (THRE) t Delay from Initial INTR Reset IRS to Transmit Start t ...
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Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) Note 1 See Write Cycle Timing Note 2 See Read Cycle Timing Read Cycle Write Cycle Transmitter Timing 9426 – ...
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Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) Note 1 See Write Cycle Timing Note 2 See Read Cycle Timing Receiver Timing MODEM Control Timing 9426– 9426– ...
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Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) RCVR FIFO First Byte (This Sets RDR) RCVR FIFO Bytes Other Than the First Byte (RDR Is Already Set) Receiver Ready FCR0 Note 1 This ...
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Timing Waveforms All timings are referenced to valid 0 and valid 1 (Continued) Receiver Ready FCR0 Note 1 This is the reading of the last byte in the FIFO Note 2 If FCR0 RCLKs e ...
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Block Diagram of a Single Channel 9426 – 16 ...
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Pin Descriptions The following describes the function of all DUART pins Some of these descriptions reference internal circuits In the following descriptions a low represents a logic 0 (0V nominal) and a high represents a logic 1 ( ...
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Pin Descriptions (Continued) RI1 RI2 (Ring Indicator) pins 43 31 When low this indi- cates that a telephone ringing signal has been received by the MODEM or data set The RI signal is a MODEM status input whose ...
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Registers DLAB1 CHSL DLAB2 CHSL ...
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14 ...
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Registers (Continued) Two identical register sets one for each channel are in the DUART All register descriptions in this section apply to the register sets in both channels 8 1 LINE CONTROL REGISTER The system programmer specifies the ...
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Registers (Continued) TABLE III DUART Reset Configuration Register Signal Interrupt Enable Register Interrupt Identification Register FIFO Control Line Control Register MODEM Control Register Line Status Register MODEM Status Register Alternate Function Register SOUT INTR (RCVR Errs) INTR (RCVR ...
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Registers (Continued) Bit 4 This bit is the Break Interrupt (BI) indicator Bit 4 is set to a logic 1 whenever the received data input is held in the Spacing (logic 0) state for longer than a full ...
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Registers (Continued) RXRDY Mode 1 In the FIFO Mode (FCR0 FCR3 1 and the trigger level or the timeout has been e reached the RXRDY pin will go low active Once it is acti- vated it will go ...
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Registers (Continued INTERRUPT ENABLE REGISTER This register enables five types of interrupts for the associ- ated serial channel Each interrupt can individually activate the interrupt (INTR) output signal It is possible to totally disable the interrupt ...
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Registers (Continued) Bits 1 and 2 These select the output signal that will be present on the multi-function pin MF These bits are individ- ually programmable for each channel so that different sig- nals can be selected on ...
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21 ...
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