ISD5216EYI Nuvoton Technology Corporation of America, ISD5216EYI Datasheet - Page 44

• Manufacturer Part Number: ISD5216EYI
• Description: IC VOICE REC/PLAY 8-16MIN 28TSOP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: ISL5216r

Specifications of ISD5216EYI

• Interface: I²C
• Filter Pass Band: 1.8 ~ 3.7kHz
• Duration: 8 ~ 16 Min
• Mounting Type: Surface Mount
• Package / Case: 28-TSOP
• For Use With: ISD-ES511 - EVALUATION SYSTEM FOR ISD5100ISD-ES501 - EVALUATION SYSTEM FOR ISD5008
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2. Send Slave Address with /W bit = “0” (Write).
9. Send Slave Address with /W bit = “0” (Write).
1. Host executes I
3. Send Digital Erase command (d1h)
4. Send high address byte (00h)
5. Send low address byte (a0h) - erase row 5 in this example. Erase operations must be
6. Host executes I
7. Wait until the desired number of pages have been erased. There will be a pulse on the RAC
8. Host executes I
10. Send the Stop command (c0h).
11. Host executes I
1. I
2. Host processor must count RAC cycles to determine where the chip is in the erase
3. 4.When the erase of the last desired row begins, the following STOP command
S
addressed on a page boundary. The 5 LSB bits of the Low Address Byte will be
ignored.
pin for each page that is erased. After the stop command (described below) has been
received, erasing will stop at the end of the page currently being erased. To erase one page
only, issue the stop command immediately after the start erase command.
7.10.6. Digital Erase
Notes:
time to execute the STOP command that causes the end of the Erase operation.
process, one row per RAC cycle. RAC pulses LOW for 0.25 microsecond at the end of
each erased row. The erase of the “next” row begins with the rising edge of RAC.
See the Digital Erase RAC timing diagram on page 46.
(Command Byte = 80 hex) must be issued. This command must be completely given,
including receiving the ACK from the Slave before the RAC pin goes HIGH .25
microseconds before the end of the row
2
C bus is released while erase proceeds. Other devices may use the bus until it is
SLAVE ADDRESS
"N" RAC cycles
Note 3.
2
2
2
2
C START.
C STOP.
C START.
C STOP
Command Byte
W
Last erased row
Note 4.
A
D1h
A
High Addr. Byte
S
- 44 -
.
DATA
SLAVE ADDRESS
A
Erase starts on falling
DATA
Low Addr. Byte
edge of Slave
acknowledge
Command Byte
W
A
P
A
Note 2
80h
ISD5216
A
P