MT47H32M16HR-25AT:FTR Micron Technology Inc, MT47H32M16HR-25AT:FTR Datasheet - Page 114

• Manufacturer Part Number: MT47H32M16HR-25AT:FTR
• Manufacturer: Micron Technology Inc

Specifications of MT47H32M16HR-25AT:FTR

• Lead Free Status / Rohs Status: Compliant

SELF REFRESH
PDF: 09005aef82f1e6e2
512MbDDR2.pdf - Rev. R 12/10 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
refresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before
applying any other command.
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
114
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
512Mb: x4, x8, x16 DDR2 SDRAM
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
© 2004 Micron Technology, Inc. All rights reserved.
t
CK after entering self
SELF REFRESH
t
CK