AGLN125V2-VQG100 Actel, AGLN125V2-VQG100 Datasheet - Page 59

• Manufacturer Part Number: AGLN125V2-VQG100
• Manufacturer: Actel

Figure 2-16 • Output Enable Register Timing Diagram
Table 2-68 • Output Enable Register Propagation Delays
CLK
D_Enable
Preset
EOUT
Clear
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
Note:
OECLKQ
OESUD
OEHD
OECLR2Q
OEPRE2Q
OEREMCLR
OERECCLR
OEREMPRE
OERECPRE
OEWCLR
OEWPRE
OECKMPWH
OECKMPWL
For specific junction temperature and voltage supply levels, refer to
values.
Output Enable Register
Timing Characteristics
Commercial-Case Conditions: T
Clock-to-Q of the Output Enable Register
Data Setup Time for the Output Enable Register
Data Hold Time for the Output Enable Register
Asynchronous Clear-to-Q of the Output Enable Register
Asynchronous Preset-to-Q of the Output Enable Register
Asynchronous Clear Removal Time for the Output Enable Register
Asynchronous Clear Recovery Time for the Output Enable Register
Asynchronous Preset Removal Time for the Output Enable Register
Asynchronous Preset Recovery Time for the Output Enable Register
Asynchronous Clear Minimum Pulse Width for the Output Enable Register
Asynchronous Preset Minimum Pulse Width for the Output Enable Register
Clock Minimum Pulse Width HIGH for the Output Enable Register
Clock Minimum Pulse Width LOW for the Output Enable Register
1.5 V DC Core Voltage
50%
1
50%
t
OESUD
50%
t
0
OECLKQ
t
50%
OEHD
50%
50%
t
OEWPRE
J
= 70°C, Worst-Case V
t
OEPRE2Q
A dv a n c e v 0. 3
50%
50%
Description
t
50%
OERECPRE
50%
t
t
OEWCLR
OECLR2Q
50%
50%
CC
= 1.425 V
IGLOO nano DC and Switching Characteristics
t
50%
OERECCLR
Table 2-6 on page 2-6
50%
t
OECKMPWH
t
OEREMPRE
50%
50%
t
OECKMPWL
for derating
0.75
0.51
0.00
1.13
1.13
0.00
0.24
0.00
0.24
0.19
0.19
0.31
0.28
Std.
t
OEREMCLR
50%
50%
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 - 45