MWS5101EL2 Intersil Corporation, MWS5101EL2 Datasheet

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MWS5101EL2

Manufacturer Part Number
MWS5101EL2
Description
Manufacturer
Intersil Corporation
Datasheet

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MWS5101EL2
Manufacturer:
HARRIS
Quantity:
1 017
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Industry Standard Pinout
• Very Low Operating Current . . . . . . . . . . . . . . . . . . 8mA
• Two Chip Select Inputs Simple Memory Expansion
• Memory Retention for Standby. . . . . . . . . . . . . 2V (Min)
• Output Disable for Common I/O Systems
• Three-State Data Output for Bus Oriented Systems
• Separate Data Inputs and Outputs
• TTL Compatible (MWS5101A)
Pinout
Ordering Information
PDIP
SBDIP
Burn-In
Burn-In
at V
Battery Voltage
PACKAGE
DD
= 5V and Cycle Time = 1 s
DO1
V
DI1
DI2
A3
A2
A1
A0
A5
A6
A7
SS
MWS5101, MWS5101A
10
11
1
2
3
4
5
6
7
8
9
(PDIP, SBDIP)
TEMP. RANGE
0
0
TOP VIEW
o
o
C to +70
C to +70
|
Copyright
o
o
C
C
22
21
20
19
18
17
16
15
14
13
12
©
V
A4
R/W
CSI
O.D.
CS2
DO4
DI4
DO3
DI3
DO2
MWS5101EL2
Intersil Corporation 1999
DD
MWS5101
250ns
-
MWS5101ELS
MWS5101DL3X
6-56
350ns
Description
The MWS5101 and MWS5101A are 256 word by 4-bit static
random access memories designed for use in memory
systems where high speed, very low operating current, and
simplicity in use are desirable. They have separate data
inputs and outputs and utilize a single power supply of 4V to
6.5V. The MWS5101 and MWS5101A differ in input voltage
characteristics (MWS5101A is TTL compatible).
Two Chip Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems by forcing the output into a high impedance state
during a write operation independent of the Chip Select input
condition. The output assumes a high impedance state
when the Output Disable is at high level or when the chip is
deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5V operation,
excellent system noise margin is preserved by using an
external pull-up resistor at each input.
For applications requiring wider temperature and operating
voltage ranges, the mechanically and functionally equivalent
static RAM, CDP1822 may be used.
The MWS5101 and MWS5101A types are supplied in 22
lead hermetic dual-in-line, sidebrazed ceramic packages (D
suffix), in 22 lead dual-in-line plastic packages (E suffix), and
in chip form (H suffix).
MWS5101AEL2
MWS5101A
250ns
-
MWS5101A
MWS5101,
MWS5101AEL3
MWS5101AEL3X E22.4
MWS5101ADL3
350ns
256-Word x 4-Bit
LSI Static RAM
File Number
E22.4
D22.4A
D22.4A
PKG. NO.
1106.2

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MWS5101EL2 Summary of contents

Page 1

... O. chip form (H suffix). CS2 17 DO4 16 DI4 15 DO3 14 DI3 13 DO2 12 MWS5101 250ns 350ns C MWS5101EL2 MWS5101ELS C - MWS5101DL3X © Intersil Corporation 1999 6-56 MWS5101, MWS5101A 256-Word x 4-Bit LSI Static RAM MWS5101A 250ns 350ns PKG. NO. MWS5101AEL2 MWS5101AEL3 E22.4 MWS5101AEL3X E22.4 ...

Page 2

CHIP SELECT 1 MODE ( Read 0 Write 0 Write 0 Standby 1 Standby X Output Disable X NOTE: Logic 1 = High, Logic 0 = Low Don’t Care. Functional Block Diagram † 4 (32) (5) ...

Page 3

Absolute Maximum Ratings DC Supply Voltage Range (All Voltages Referenced to V Terminal -0.5V to +7V SS Input Voltage Range, All Inputs . . . . . . . ...

Page 4

Dynamic Electrical Specifications PARAMETER SYMBOL READ CYCLE TIMES (FIGURE 1) Read Cycle t Access from Address t Output Valid from Chip Select 1 t DOA1 Output Valid from Chip Select 2 t DOA2 Output Valid from Output Disable t DOA3 ...

Page 5

CHIP SELECT 1 CHIP SELECT 2 OUTPUT DISABLE READ/WRITE DATA OUT IMPEDANCE A0-A7 CHIP SELECT 1 CHIP SELECT 2 OUTPUT DISABLE DI1-DI4 READ/WRITE NOTE required for common I/O operation only; for separate I/O operations, output ...

Page 6

Data Retention Specifications at T PARAMETER Minimum Data Retention Voltage Data Retention Quiescent Current L2 Types L3 Types Chip Deselect to Data Retention Time Recovery to Normal Operation Time Rise and Fall Time DD DR NOTE: o ...

Page 7

... All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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