AM7992BPC Advanced Micro Devices, AM7992BPC Datasheet

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AM7992BPC

Manufacturer Part Number
AM7992BPC
Description
Serial interface adapter (SIA)
Manufacturer
Advanced Micro Devices
Datasheet

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Am7992B
Serial Interface Adapter (SIA)
DISTINCTIVE CHARACTERISTICS
GENERAL DESCRIPTION
The Am7992B Serial Interface Adapter (SIA) is a
Manchester encoder/decoder compatible with IEEE
802.3, Cheapernet, and Ethernet specifications. In an
IEEE 802.3/Ethernet application, the Am7992B inter-
faces the Am7990 Local Area Network Controller for
Ethernet (LANCE) to the Ethernet transceiver device,
BLOCK DIAGRAM
Publication# 03378
Issue Date: May 1993
Compatible with lEEE 802.3/Ethernet/Cheapernet
specifications
Crystal/TTL oscillator-controlled Manchester
encoder
Manchester decoder acquires clock and data
within four bit times with an accuracy of 3 ns
Guaranteed carrier and collision detection
squelch threshold limits
— Carrier/collision detected for inputs greater than
— No carrier/collision for inputs less than –175 mV
–275 mV
Transmit Enable (TENA)
Carrier Present (RENA)
Transmit Clock (TCLK)
Receive Clock (RCLK)
Transmit Data (TX)
Receive Data (RX)
FINAL
Collision (CLSN)
Rev: I
Amendment/0
20 MHz
Manchester
Decoder
Collision
Carrier
Detect
Detect
XTAL
XTAL
1
2
Manchester
Encoder
Crystal
OSC
acquires clock and data within four bit times, and de-
codes Manchester data with worst case 19 ns phase
jitter at 10 MHz. SIA provides both guaranteed signal
threshold limits and transient noise suppression cir-
cuitry in both data and collision paths to minimize false
start conditions.
Input signal conditioning rejects transient noise
— Transients <10 ns for collision detector inputs
— Transients <20 ns for carrier detector inputs
Receiver decodes Manchester data with worst
case 19 ns of clock jitter (at 10 MHz)
TTL-compatible host interface
Transmit accuracy +0.01% (without adjustments)
Receiver
Reject
Reject
Noise
Noise
Filter
Filter
Data
Receive+
Receive–
Collision+
Collision–
Transmit+
Transmit–
03378I-1
1

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AM7992BPC Summary of contents

Page 1

FINAL Am7992B Serial Interface Adapter (SIA) DISTINCTIVE CHARACTERISTICS Compatible with lEEE 802.3/Ethernet/Cheapernet specifications Crystal/TTL oscillator-controlled Manchester encoder Manchester decoder acquires clock and data within four bit times with an accuracy Guaranteed carrier and collision detection squelch threshold ...

Page 2

RELATED PRODUCTS Part No. Description Am7990 Local Area Network Controller for Ethernet (LANCE) Am7996 IEEE 802.3/Ethernet/Cheapernet/Transceiver Am79C900 Integrated Local Area Communications Controller CONNECTION DIAGRAMS DIP 1 24 Collision+ CLSN 2 23 Collision– RX Receive+ RENA Receive– ...

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ORDERING INFORMATION Standard Products AMD standard products are available in several packages and operating ranges. The order number (valid combination) is formed by a combination of the elements below. AM7992B DEVICE NUMBER/DESCRIPTION Am7992B Serial Interface Adapter Valid Combinations DC, DCB, ...

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PIN DESCRIPTION CLSN Collision (Output, TTL Active HIGH) Signals at the Collision terminals meeting threshold and pulse-width requirements will produce a logic HIGH at CLSN output. When no signal is present at Collision , CLSN output will be LOW. RX ...

Page 5

Biased Crystal Oscillator (Input the input and X is the bypass port. When con nected for crystal operation, the system clock that ap- pears at TCLK is half the frequency of ...

Page 6

FUNCTIONAL DESCRIPTION The Am7992B serial interface adapter (SIA) has three basic functions Manchester encoder/line driver in the transmit path, a Manchester decoder with noise filtering and quick lock-on characteristics in the receive path, and a signal detector/converter ...

Page 7

ALS Driver or Equivalent Figure 3. TTL Clock Driver Circuit for X SIA Oscillator Specification for External Crystal When using a crystal to drive the Am7992B oscillator, the following crystal specification should be used to en- sure a transmit accuracy ...

Page 8

RX Q RCLK Clock Gating RENA Input Signal Conditioning The Carrier Receiver detects the presence of an in- coming data packet by discerning and rejecting noise from expected Manchester data. It also controls the stop and start of the phase-locked ...

Page 9

INTCARR deassert allows the last bit to be strobed by RCLK and trans- ferred by the LANCE without an extra bit at the end of the message. When RENA deasserts (see Receive Timing—End ...

Page 10

Jitter Tolerance Definition and Test The Receive Timing—Start of Reception Clock Acqui- sition waveform diagram shows the internal timing rela- tionships implemented for decoding Manchester data in the Am7992B. The Am7992B utilizes a clock capture circuit to align its internal ...

Page 11

AMD APPLICATION ETHERNET Local Local CPU Memory Local Bus AUI – Attachment Unit Interface DTE – Data Terminal Equipment MAU – Medium Attachment Unit CHEAPERNET Local Local CPU Memory Local Bus AUI Cable DTE Am7990 Am7992B LANCE SIA DTE Am7990 ...

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ABSOLUTE MAXIMUM RATINGS Storage Temperature . . . . . . . . . . . Ambient Temperature with Power Applied . . . . . . . . . . . . . . . . . . . ...

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AMD DC CHARACTERISTICS over operating ranges unless otherwise specified Parameter Symbol Parameter Description V Output HIGH Voltage RX, OH RENA, CLSN, TCLK, RCLK V Output LOW Voltage OL RCLK, TSEL, TCLK, RENA, RX, CLSN V Differential Output Voltage TX+ > ...

Page 14

SWITCHING CHARACTERISTICS over operating ranges unless otherwise specified No. Parameters Description Receiver Specification 1 t RCLK Cycle Time RCT 2 t RCLK HIGH Time RCH 3 t RCLK LOW Time RCL 4 t RCLK Rise Time RCR 5 t RCLK ...

Page 15

AMD SWITCHING CHARACTERISTICS (continued) No. Parameters Description Transmitter Specification 24 t TCLK LOW Time TCL 25 t TCLK HIGH Time TCH 26 t TCLK Rise Time TCR 27 t TCLK Rise Time TCF and TENA ...

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KEY TO SWITCHING WAVEFORMS 16 WAVEFORM INPUTS OUTPUTS Must be Will be Steady Steady May Will be Change Changing from from May Will be Change Changing from from ...

Page 17

AMD SWITCHING WAVEFORMS Bit Cell 1 1 Receive (Note A) (Note E) (Measured Differentially) BCC 1 INTCARR 10 RENA V Enable INTRCLK (Note B) RCK Enable RCLK RX INTPLLCLK Notes: A. Minimum Width > 45 ns. B. ...

Page 18

SWITCHING WAVEFORMS Bit (N – 1) Receive+ (Measured Differentially) BCC INTCARR RENA V Enable INTRCLK RCK Enable RCLK RX PLL CLK Notes: A. INTCARR deasserts 1.55 bit times after last Receive Rising Edge. B. Start of Next ...

Page 19

AMD SWITCHING WAVEFORMS 0 Bit (N – 1) Receive (Measured Differentially) BCC INTCARR V Enable INTRCLK RCK Enable RCLK RX RENA PLL CLK Note: A. INTCARR deasserts 1.55 bit times after last Receive Rising Edge. Receive Timing ...

Page 20

SWITCHING WAVEFORMS (Note A) X1 TCLK TENA TX (Note B) TSEL Transmit+ (Note C) Transmit– (Note C) Transmit (Measured Differentially) (Note B) Notes MHz Sine Wave from Crystal Oscillator or driven with X1 driven from External Source ...

Page 21

AMD SWITCHING WAVEFORMS X1 TCLK TENA TSEL CASE 1 TX (Last Bit = 0) Transmit+ Transmit– Transmit (Measured Differentially Bit (N – 2) BCC CASE 2 TX (Last Bit = 1) Transmit+ Transmit– Transmit ...

Page 22

SWITCHING WAVEFORMS 0 V Collision Presence – 22 CLSN X1 TCLK TENA Transmit (Measured Differentially Max IDC 2.0 V Collision Timing Transmit Timing (at start of packet) Am7992B AMD V Max IDC ...

Page 23

AMD SWITCHING WAVEFORMS Receive (Measured Differentially) V Min IDC (–175 mV) V Max IDC (–275 mV) RENA Collision (Measured Differentially) V Min IDC (–175 mV) V Max IDC (–275 mV) CLSN 2 4 RCLK IRVD 0 V ...

Page 24

SWITCHING WAVEFORMS TCLK TX TENA X1 Driving 1.5 Input t HIGH TCLK 0.8 35 Transmit+, Transmit– (Note A) Note: A. Encode Manchester clock transition (BCC) at Point ‘A’ and bit cell edge (BCB) at point ‘B’. *See Specification for External ...

Page 25

AMD SWITCHING WAVEFORMS Bit Number INTRCLK PLL CLK 4.5 V Receive+ 1 Receive– 0 (Note A) +4.5 V Receive 1 –1 Receive+ 0 +4.5 V Receive– +1.5 V (Note B) +1.5 ...

Page 26

TYPICAL PERFORMANCE CURVE 600 500 400 Differential Output Voltage (V ) 300 O (mV) 200 100 0 –100 End of Transmission – Differential Output Voltage* *Equivalent Load: Notes: 1. 802.3 Test Load: 2. 802.3 10BASE5 Network Connection: 3. 802.3 10BASE2 ...

Page 27

AMD SWITCHING TEST CIRCUITS DUT 50 pF 03378I-27 A. Test Load for RX, RENA, RCLK, TCLK, CLSN DUT Transmit+ DUT Transmit– B. Transmit Output + – DC Voltage C. Receive and Collision Input Am7992B 03378I-28 03378I-29 ...

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