CXL5502P Sony, CXL5502P Datasheet

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CXL5502P

Manufacturer Part Number
CXL5502P
Description
CMOS-CCD 1H Delay Line for NTSC
Manufacturer
Sony
Datasheet
For the availability of this product, please contact the sales office.
Description
that provide 1H delay time for NTSC signals including
the external low-pass filter.
Features
• Single power supply (5V)
• Low power consumption 95mW (Typ.)
• Built-in peripheral circuits
• Clamp level of I/O signal can be selected
• Built-in quadruple PLL circuit
Functions
• 905-bit CCD register
• Clock driver
• Autobias circuit
• Input clamp circuit
• Sample and hold circuit
• PLL circuit (quadruple progression)
Structure
The CXL5502M/N/P are CMOS-CCD delay line ICs
The ICs contain a PLL circuit (quadruple progression).
CMOS-CCD
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
CMOS-CCD 1H Delay Line for NTSC
– 1 –
CXL5502M/N/P
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
• Operating temperature Topr
• Storage temperature
• Allowable power dissipation
Recommended Operating Condition (Ta = 25°C)
Recommended Clock Conditions (Ta = 25°C)
• Input clock amplitude
• Clock frequency
• Input clock waveform
Input Signal Amplitude
V
Supply voltage
14 pin SOP (Plastic)
SIG
CXL5502M
500mVp-p (Typ.), 572mVp-p (Max.)
(at internal clamp condition)
14 pin DIP (Plastic)
CXL5502P
V
Tstg
P
CXL5502M
CXL5502N
CXL5502P
V
V
f
Sine wave
CLK
DD
D
DD
CLK
16 pin SSOP (Plastic)
CXL5502N
–55 to +150
0.3 to 1.0
3.579545
–10 to +60
5 ± 5%
(0.5Vp-p typ.)
E89930E79-PS
6
400
260
800
Vp-p
MHz
mW
mW
mW
°C
°C
V
V

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CXL5502P Summary of contents

Page 1

... Absolute Maximum Ratings (Ta = 25°C) • Supply voltage V • Operating temperature Topr • Storage temperature Tstg • Allowable power dissipation P CXL5502M CXL5502N CXL5502P Recommended Operating Condition (Ta = 25°C) Supply voltage V Recommended Clock Conditions (Ta = 25°C) • Input clock amplitude V • Clock frequency f CLK • ...

Page 2

Block Diagram and Pin Configuration (Top View) CXL5502M Autobias circuit (905bit) Clamp circuit I/O1 CXL5502N Autobias circuit (905bit) Clamp circuit I/O1 VCO V IN ...

Page 3

Pin Description CXL5502M/P Pin No. Symbol OUT — — VCO OUT O 8 CLK — ...

Page 4

Description of Function In the CXL5502M/N/P, the condition of I/O control pins (Pins 2 and 3) control the input signal clamp condition and the mode of the output signal with relation to its input signal. There are 2 modes for ...

Page 5

Electrical Characteristics Item Symbol Test condition IDDPN Supply current IDDNP Low GLPN 200kHz, frequency 500mVp-p, GLNP gain sine wave fPN 200kHz Frequency 150mVp-p, response fNP sine wave DGPN 5-staircase wave Differential (See Note 5) gain DGNP DPPN 5-staircase wave Differential ...

Page 6

This is the IC supply current value during clock and signal input. (3) GLPN, GLNP are output gain of OUT pin when a 500mVp-p, 200kHz sine wave is fed to IN pin. (Example of calculation) GLPN = 20 log ...

Page 7

S/N ratio during a 50% white video signal input shown in figure below is tested at a video noise meter, in BPF 100kHz to 4MHz, Sub Carrier Trap mode. Input waveform (Input waveform of NP mode is the inverted ...

Page 8

CXL5502M/N/P ...

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CXL5502M/N/P ...

Page 10

Example of Representative Characteristics Supply current vs. Ambient temperature – Ambient temperature [°C] Frequency response vs. Ambient temperature 0 –1 –2 –3 – Ambient temperature [°C] Supply current vs. Supply voltage ...

Page 11

Frequency response vs. Supply voltage 0 –1 –2 –3 4.75 5 Supply voltage [ –2 –4 –6 10k Differential gain vs. Supply voltage 5.25 4.75 Frequency response 100k Frequency [Hz] – 11 ...

Page 12

... Package Outline Unit: mm CXL5502M 0.45 ± 0.1 SONY CODE EIAJ CODE JEDEC CODE 1.44 MAX SONY CODE EIAJ CODE JEDEC CODE 14PIN SOP (PLASTIC) + 0.4 9.9 – 0 1.27 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT SOP-14P-L01 LEAD MATERIAL SOP014-P-0300 PACKAGE MASS 14PIN SOP (Plastic) 300mil 10.2 ± ...

Page 13

... NOTE: Dimension “ ” does not include mold protrusion. SONY CODE SSOP-16P-L01 EIAJ CODE SSOP016-P-0044 JEDEC CODE CXL5502P + 0.4 19.2 – 0 2.54 0.5 ± 0.1 1.2 ± 0.15 SONY CODE EIAJ CODE JEDEC CODE 16PIN SSOP (PLASTIC) 1.25 – ...

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