HT48R10A-1 Holtek, HT48R10A-1 Datasheet
HT48R10A-1
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HT48R10A-1 Summary of contents
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... Watchdog Timer 1024 14 program memory ROM General Description The HT48R10A-1/HT48C10-1 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48C10-1 is fully pin and functionally compatible with the OTP version HT48R10A-1 device ...
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... Block Diagram Pin Assignment Rev. 1.90 HT48R10A-1/HT48C10-1 2 November 4, 2005 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 1.90 HT48R10A-1/HT48C10-1 Description +6.0V Storage Temperature ............................ 125 ...
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... Input Low Voltage (RES) IL2 V Input High Voltage (RES) IH2 V Low Voltage Reset LVR I I/O Port Sink Current OL I I/O Port Source Current OH R Pull-high Resistance PH Rev. 1.90 HT48R10A-1/HT48C10-1 Test Conditions Min. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V No load, f =4MHz SYS ...
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... WDT2 (System Clock) Watchdog Time-out Period t WDT3 (RTC OSC) t External Reset Low Pulse Width RES t System Start-up Timer Period SST t Interrupt Pulse Width INT Rev. 1.90 HT48R10A-1/HT48C10-1 Test Conditions Min. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 400 3.3V~5.5V 400 3.2MHz 1800 1 ...
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... Return from Subroutine S9 Note: *9~*0: Program counter bits #9~#0: Instruction code bits Rev. 1.90 HT48R10A-1/HT48C10-1 When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- set, internal interrupt, external interrupt or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction ...
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... Note: *9~*0: Table location bits @7~@0: Table pointer bits Rev. 1.90 HT48R10A-1/HT48C10-1 ferred to the lower portion of TBLH, and the remaining 2 bits are read The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP read/write register (07H), which indicates the table location ...
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... PBC;15H, PCC;17H). The remain- ing space before the 40H is reserved for future ex- RAM Mapping Rev. 1.90 HT48R10A-1/HT48C10-1 panded usage and reading these locations will get 00H . The general purpose data memory, addressed from 40H to 7FH, is used for data and control informa- tion under instruction commands ...
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... Unused bit, read Unused bit, read as 0 Rev. 1.90 HT48R10A-1/HT48C10-1 (STATUS) are altered by the interrupt service program which corrupts the desired control sequence, the con- tents should be saved in advance. External interrupts are triggered by a high to low transi- tion of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set ...
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... No matter what oscillator type is selected, the signal provides the system clock. The HALT mode stops the system oscillator and ignores an external signal to conserve power. Rev. 1.90 HT48R10A-1/HT48C10-1 Function INTC (0BH) Register oscillator is used, an external resistor between OSC1 and VDD is required and the resistance must range from 24k to 1M ...
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... CLR WDT times selection option . If the CLR WDT is selected (i.e. CLRWDT times equal Rev. 1.90 HT48R10A-1/HT48C10-1 Watchdog Timer one), any execution of the CLR WDT instruction will clear the WDT. In the case that CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two instructions must be executed to clear the WDT ...
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... SST delay. An extra option load time delay is added during system reset (power-up, WDT time-out at normal mode or RES reset). Rev. 1.90 HT48R10A-1/HT48C10-1 Reset Timing Chart Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference ...
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... To define the operating mode 01=Event count mode (external clock) 6 TM0 10=Timer mode (internal clock) 7 TM1 11=Pulse width measurement mode 00=Unused Rev. 1.90 HT48R10A-1/HT48C10-1 RES Reset RES Reset (Normal Operation) (HALT) xxxx xxxx xxxx xxxx 00-0 1000 00-0 1000 000H -uuu uuuu ...
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... TMRC) should be set the pulse width measurement mode, the TON will be cleared au- tomatically after the measurement cycle is completed. Rev. 1.90 HT48R10A-1/HT48C10-1 Timer/Event Counter But in the other two modes the TON can only be reset by instructions. The overflow of the timer/event counter is one of the wake-up sources ...
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... B buzzer option BZ, x don't care C CMOS output Rev. 1.90 HT48R10A-1/HT48C10-1 mented; on reading them returned whereas writing then results in a no-operation. See Application note. There is a pull-high option available for all I/O ports (byte option). Once the pull-high option of an I/O port is se- lected, all I/O lines have pull-high resistors ...
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... Since the low voltage has to maintain in its original state and exceed 1ms, therefore 1ms delay enter the reset mode. Rev. 1.90 HT48R10A-1/HT48C10-1 The LVR uses the OR function with the external RES signal to perform chip reset. The relationship between V ...
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... PA CMOS or Schmitt input 6 PA, PB, PC pull-high enable or disable (By port) 7 BZ/BZ enable or disable 8 LVR enable or disable System oscillator 9 Ext.RC, Ext.crystal, Int.RC+RTC or Int.RC+PC3/PC4 10 Int.RC frequency selection 3.2MHz, 1.6MHz, 800kHz or 400kHz Rev. 1.90 HT48R10A-1/HT48C10-1 Options /4 or RTC oscillator or disable SYS or RTCOSC SYS 17 November 4, 2005 ...
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... The function of the resistor ensure that the oscillator will switch off should low voltage condi- tions occur. Such a low voltage, as mentioned here, is one which is less than the lowest value of the MCU operating voltage. Note however that if the LVR is enabled then R1 can be removed. Rev. 1.90 HT48R10A-1/HT48C10-1 C1, C2 0pF 10pF ...
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... Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 1.90 HT48R10A-1/HT48C10-1 Description 19 Instruction Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 1.90 HT48R10A-1/HT48C10-1 Description 20 Instruction Flag Cycle Affected 2 None ...
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... ACC ACC+x Affected flag(s) TO ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF PDF PDF OV ...
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... The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack Program Counter+1 Program Counter Affected flag(s) TO CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF PDF addr PDF ...
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... WDT 00H* PDF and TO Affected flag( CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF PDF ...
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... Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C=C PDF ...
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... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation Program Counter Affected flag(s) TO MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 Program Counter+1 PDF PDF PDF addr ...
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... Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF Program Counter+1 PDF ...
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... Description Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) ACC.0 [m].7 Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 Stack PDF Stack PDF OV Z ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF [m].i; [m].i:bit i of the data memory (i=0~6) PDF PDF OV ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF OV Z ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF PDF ...
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... The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF PDF ...
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... XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO Rev. 1.90 HT48R10A-1/HT48C10-1 PDF PDF PDF OV ...
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... Package Information 24-pin SKDIP (300mil) Outline Dimensions Symbol Rev. 1.90 HT48R10A-1/HT48C10-1 Dimensions in mil Min. Nom. 1235 255 125 125 16 50 100 295 345 0 34 Max. 1265 265 135 145 20 70 315 360 15 November 4, 2005 ...
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... SOP (300mil) Outline Dimensions Symbol Rev. 1.90 HT48R10A-1/HT48C10-1 Dimensions in mil Min. Nom. 394 290 14 590 Max. 419 300 20 614 104 November 4, 2005 ...
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... Reel Dimensions SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 1.90 HT48R10A-1/HT48C10-1 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 36 November 4, 2005 ...
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... Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 1.90 HT48R10A-1/HT48C10-1 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.90 HT48R10A-1/HT48C10-1 38 November 4, 2005 ...