DS1000-175 Dallas Semiconductor, DS1000-175 Datasheet

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DS1000-175

Manufacturer Part Number
DS1000-175
Description
5-Tap Silicon Delay Line
Manufacturer
Dallas Semiconductor
Datasheet
FEATURES
DESCRIPTION
The DS1000 series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These
devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively,
8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP
packages are available with hybrid lead configurations. The DS1000 series delay lines provide a nominal
accuracy of 5% or 2 ns, whichever is greater. The DS1000 5-Tap Silicon Delay Line reproduces the
input logic state at the output after a fixed delay as specified by the extension of the part number after the
dash. The DS1000 is designed to reproduce both leading and trailing edges with equal precision. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call 972-371-4348.
www.dalsemi.com
All-silicon time delay
5 taps equally spaced
Delays are stable and precise
Both leading and trailing edge accuracy
Delay tolerance 5% or 2 ns, whichever is
greater
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Fast turn prototypes
Extended temperature range available
(DS1000-IND)
TAP 2
TAP 4
DS1000 14-Pin DIP (300-mil)
1 of 5
GND
See Mech. Drawings Section
NC
NC
NC
IN
PIN ASSIGNMENT
PIN DESCRIPTION
TAP 1-TAP 5 - TAP Output Number
V
GND
NC
IN
1
2
3
4
5
6
7
CC
5-Tap Silicon Delay Line
13
12
14
11
10
9
8
NC
V
NC
NC
TAP 1
TAP 3
TAP 5
- +5 Volts
- Ground
- No Connection
- Input
CC
TAP 2
TAP 2
TAP 4
TAP 4
DS1000M 8-Pin DIP (300-mil)
DS1000Z 8-Pin SOIC (150-mil)
GND
GND
See Mech. Drawings Section
See Mech. Drawings Section
IN
IN
1
2
3
4
1
2
3
4
DS1000
8
7
6
5
8
7
6
5
111799
V
V
TAP 1
TAP 3
TAP 5
TAP 1
TAP 3
TAP 5
CC
CC

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DS1000-175 Summary of contents

Page 1

... DESCRIPTION The DS1000 series delay lines have five equally spaced taps providing delays from 500 ns. These devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively, 8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and industry standard DIP and SOIC packaging ...

Page 2

... CC TYP MAX UNITS 5. 0 25° ± 5 TYP MAX UNITS ns Table 1 ns Table 1 ns 100 ms ns DS1000 TAP 5 TOLERANCE Init Temp 1.1 2 1.2 2.3 1.4 2.5 1.5 3 1.8 3.8 2 6.3 3.8 7.5 4.5 8.8 5 12.5 7 NOTES ...

Page 3

... TAP 5 delay. Only a -25 operating with a 40-ns period and V CC 5.25V will have mA. For example a -100 will never exceed 30 mA, etc. CC 10. See “Test Conditions” section at the end of this data sheet. TIMING DIAGRAM: SILICON DELAY LINE Figure 2 MIN 25°C) A TYP MAX UNITS DS1000 NOTES = CC ...

Page 4

... TEST SETUP DESCRIPTION Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1000. The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected between the input and each tap ...

Page 5

... OUTPUT: Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on the rising and falling edge. NOTE: Above conditions are for test only and do not restrict the operation of the device under other data sheet conditions DS1000 ...

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