MC54HC4538AJ Motorola, MC54HC4538AJ Datasheet

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MC54HC4538AJ

Manufacturer Part Number
MC54HC4538AJ
Description
Dual precision monostable multivibrator
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual Precision
Monostable Multivibrator
(Retriggerable, Resettable)
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
or the negative edge of an input pulse, and produces a precision output
pulse over a wide range of pulse widths. Because the device has conditioned
trigger inputs, there are no trigger–input rise and fall time restrictions. The
output pulse width is determined by the external timing components, R x and
C x . The device has a reset function which forces the Q output low and the Q
output high, regardless of the state of the output pulse circuitry.
10/95
TRIGGER
INPUTS
Motorola, Inc. 1995
The MC54/74HC4538A is identical in pinout to the MC14538B. The device
This dual monostable multivibrator may be triggered by either the positive
Unlimited Rise and Fall Times Allowed on the Trigger Inputs
Output Pulse is Independent of the Trigger Pulse Width
Same Test Jig)
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 3.0 to 6.0 V
Low Input Current: 1.0 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 145 FETs or 36 Equivalent Gates
PIN 16 = V CC
PIN 8 = GND
R X AND C X ARE EXTERNAL COMPONENTS
PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND
10% Guaranteed Pulse Width Variation from Part to Part (Using the
RESET 1
A1
B1
4
5
3
C X 1
TRIGGER
1
INPUTS
LOGIC DIAGRAM
2
RESET 2
R X 1
A2
B2
6
7
12
11
13
Q1
Q1
V CC
C X 2
15
14
3–1
R X 2
10
9
Q2
Q2
V CC
MC54/74HC4538A
REV 6
16
16
Reset
16
H
H
H
H
H
H
L
1
1
C X 1/R X 1
RESET 1
MC54HCXXXXAJ
MC74HCXXXXAN
MC74HCXXXXAD
1
ORDERING INFORMATION
Inputs
GND
GND
L,H,
Q1
Q1
A1
B1
A
H
FUNCTION TABLE
L
X
L
X
X
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
L,H,
CERAMIC PACKAGE
B
H
X
H
X
X
L
PLASTIC PACKAGE
SOIC PACKAGE
CASE 751B–05
CASE 620–10
CASE 648–08
16
15
14
13
12
10
11
N SUFFIX
D SUFFIX
J SUFFIX
9
Ceramic
Plastic
SOIC
Not Triggered
Not Triggered
Not Triggered
Not Triggered
Not Triggered
V CC
GND
C X 2/R X 2
RESET 2
A2
B2
Q2
Q2
Q
L
Outputs
Q
H

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MC54HC4538AJ Summary of contents

Page 1

... Chip Complexity: 145 FETs or 36 Equivalent Gates LOGIC DIAGRAM TRIGGER 5 INPUTS B1 3 RESET 1 A2 TRIGGER INPUTS B2 RESET 2 PIN PIN 8 = GND R X AND C X ARE EXTERNAL COMPONENTS PIN 1 AND PIN 15 MUST BE HARD WIRED TO GND 10/95 Motorola, Inc. 1995 MC54/74HC4538A 3–1 J SUFFIX CERAMIC PACKAGE 16 CASE 620–10 ...

Page 2

... Power Down Considerations). Susceptibility to externally induced noise signals may occur for R x > 1 The HC4538A will function at 2.0 V but for optimum pulse width stability should be above 3.0 V. NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA Î Î Î Î Î Î ...

Page 3

... A A Î Î Î Î Î Î Î Î Î Î Î Î Î Î MOTOROLA ...

Page 4

... NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Speed CMOS Data Book (DL129/D). ...

Page 5

... CAPACITANCE ( F) Timing Capacitance MOTOROLA 100 ...

Page 6

... MC54/74HC4538A 1.1 1.05 1 0.95 0.9 0.85 0.8 – 75 1.03 1.02 1.01 1 0.99 0.98 0.97 – 75 MOTOROLA 0 – 50 – 100 AMBIENT TEMPERATURE ( C) Figure 4. Normalized Output Pulse Width versus Power Supply Voltage 0 5 4.5 V – 50 – 100 AMBIENT TEMPERATURE ( C) Figure 5. Normalized Output Pulse Width versus Power Supply Voltage 3– ...

Page 7

... PLH t PHL 50% Figure 50 90% 10% t w(L) t rec 50% 50% 50% Figure 7. TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 8. Test Circuit 3–7 MC54/74HC4538A V CC GND V CC GND V CC GND V CC GND V CC GND + t rr (RETRIGGERED PULSE) MOTOROLA ...

Page 8

... RESET POWER ON RESET MOTOROLA PIN DESCRIPTIONS tors (see the Block Diagram). Polystyrene capacitors are recommended for optimum pulse width control. Electrolytic capacitors are not recommended due to high leakages associated with these type capacitors. GND (Pins 1 and 15) External ground. The external timing capacitors discharge to ground through these pins ...

Page 9

... with a time constant (#15). Once the voltage across C x charges to above the low- er reference voltage, the lower reference circuit will go low allowing the monostable multivibrator to be retriggered. TRIGGER CYCLE (A INPUT) (B INPUT ref UPPER 18 19 Figure 10. Timing Diagram 3–9 MC54/74HC4538A RESET RETRIGGER MOTOROLA ...

Page 10

... charging up toward the reference volt- age of the upper reference circuit (#21). When a reset Figure 11. Discharge Protection During Power Down MOTOROLA occurs, the output of the reset latch goes low (#22), turning on transistor M1. Thus allowed to quickly charge (#23) to await the next trigger signal. ...

Page 11

... RECOMMENDED PULSE WIDTH RANGE High–Speed CMOS Logic Data DL129 — Rev 6 TYPICAL APPLICATIONS R X RISING–EDGE V CC TRIGGER FALLING–EDGE TRIGGER Figure 13. Non–retriggerable Monostable Circuitry ONE–SHOT SELECTION GUIDE 100 100 Limited operating voltage (2 – 3–11 MC54/74HC4538A RESET = RESET = MIN MOTOROLA ...

Page 12

... 0.25 (0.010) M –A – 0.25 (0.010) –A – –T – SEATING PLANE 0.25 (0.010 MOTOROLA OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 620–10 ISSUE V –B – 0.25 (0.010 SUFFIX PLASTIC PACKAGE CASE 648–08 ISSUE SEATING –T PLANE – SUFFIX PLASTIC SOIC PACKAGE CASE 751B– ...

Page 13

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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