DM54174J National Semiconductor, DM54174J Datasheet

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DM54174J

Manufacturer Part Number
DM54174J
Description
Manufacturer
National Semiconductor
Datasheet

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C 1995 National Semiconductor Corporation
54174 DM54174 DM74174 54175 DM54175 DM74175
Hex Quad D Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic All have a direct clear
input and the quad (175) version features complementary
outputs from each flip-flop
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the positive-
going edge of the clock pulse Clock triggering occurs at a
particular voltage level and is not directly related to the tran-
sition time of the positive-going pulse When the clock input
is at either the high or low level the D input signal has no
effect at the output
Connection Diagrams
Function Table
Order Number 54174DMQB 54174FMQB DM54174J
See NS Package Number J16A N16E or W16A
DM54174W or DM74174N
Dual-In-Line Package
(Each Flip-Flop)
TL F 6557
H
L
X
Q
0
e
e
e
e
e
e
Clear
Low Level (steady state)
175 only
High Level (steady state)
Don’t Care
Transition from low to high level
The level of Q before the indicated steady-state input conditions were established
H
H
H
L
Inputs
Clock
TL F 6557 – 1
X
L
D
X
H
X
L
Features
Y
Y
Y
Y
Y
Y
Y
Y
Order Number 54175DMQB 54175FMQB DM54175J
174 contains six flip-flops with single-rail outputs
175 contains four flip-flops with double-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include
Typical clock frequency 40 MHz
Typical power dissipation per flip-flop 38 mW
Alternate Military Aerospace device (54174 54175) is
available Contact a National Semiconductor Sales Of-
fice Distributor for specifications
Buffer storage registers
Shift registers
Pattern generators
See NS Package Number J16A N16E or W16A
Q
Q
H
L
L
0
Outputs
DM54175W or DM74175N
Dual-In-Line Package
Q
Q
H
H
L
0
RRD-B30M105 Printed in U S A
June 1989
TL F 6557 – 2

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DM54174J Summary of contents

Page 1

... When the clock input is at either the high or low level the D input signal has no effect at the output Connection Diagrams Dual-In-Line Package Order Number 54174DMQB 54174FMQB DM54174J DM54174W or DM74174N See NS Package Number J16A N16E or W16A Function Table (Each Flip-Flop) ...

Page 2

... Absolute Maximum Ratings If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage Input Voltage Operating Free Air Temperature Range DM54 and 54 b DM74 Storage Temperature Range b Recommended Operating Conditions Symbol ...

Page 3

Switching Characteristics and (See Section 1 for Test Waveforms and Output Load Symbol Parameter f Maximum Clock MAX Frequency t Propagation Delay Time PLH Low to High Level Output ...

Page 4

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter V Input Clamp Voltage High Level Output V OH Voltage V V Low Level Output V OL Voltage V I Input Current ...

Page 5

Logic Diagrams 174 TL F 6557 – 175 TL F 6557 – 4 ...

Page 6

6 ...

Page 7

... Physical Dimensions inches (millimeters) 16-Lead Ceramic Dual-In-Line Package (J) Order Number 54174DMQB 54175DMQB DM54174J or DM54175J 16-Lead Molded Dual-In-Line Package (N) Order Number DM74174N or DM74175N NS Package Number J16A NS Package Number N16E 7 ...

Page 8

... Hong Kong Ltd 49) 0-180-530 85 86 13th Floor Straight Block a Ocean Centre 5 Canton Rd 49) 0-180-530 85 85 Tsimshatsui Kowloon a Tel ( 49) 0-180-532 78 32 Hong Kong a 49) 0-180-532 93 58 Tel (852) 2737-1600 a Tel ( 49) 0-180-534 16 80 Fax (852) 2736-9960 a National Semiconductor Japan Ltd Tel 81-043-299-2309 Fax 81-043-299-2408 ...

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