K9F2G08U0A Samsung, K9F2G08U0A Datasheet
![no-image](/images/manufacturer_photos/0/5/577/samsung_sml.jpg)
K9F2G08U0A
Available stocks
Related parts for K9F2G08U0A
K9F2G08U0A Summary of contents
Page 1
... K9F2G08R0A K9F2G08U0A INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...
Page 2
... K9F2G08R0A K9F2G08U0A Document Title 256M x 8 Bit NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue 0.1 1. 1.8V part is added. 2. tRHW, tCSD parameter is defined DDP LGA part is deleted. 4. Technical note is added.(p.18) 0.2 1. FBGA package size is changed 2. 1.8V TSOP is deleted ...
Page 3
... Command Driven Operation • Intelligent Copy-Back with internal 1bit/528Byte EDC • Unique ID for Copyright Protection • Package : - K9F2G08R0A-JCB0/JIB0 : Pb-FREE PACKAGE 63 - Ball FBGA I ( 0.8 mm pitch) - K9F2G08U0A-PCB0/PIB0 : Pb-FREE PACKAGE 48 - Pin TSOP I ( 0.5 mm pitch) - K9F2G08U0A-ICB0/IIB0 52 - Pin ULGA ( 1.00 mm pitch) 3 FLASH MEMORY PKG Type ...
Page 4
... Vss 13 N.C 14 N.C 15 CLE 16 ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8° 0.45~0.75 0.018~0.030 K9F2G08U0A-PCB0/PIB0 48-pin TSOP1 38 37 Standard Type 36 35 12mm x 20mm 20.00 ±0.20 0.787 ±0.008 ...
Page 5
... K9F2G08R0A K9F2G08U0A PIN CONFIGURATION (FBGA K9F2G08R0A-JCB0/JIB0 N.C N.C N.C N.C N.C N.C N.C /WP ALE Vss /CE /WE R/B NC /RE CLE I/ Vcc NC I/O1 NC Vcc I/O5 I/O7 Vss I/O2 I/O3 I/O4 I/O6 Vss N.C N.C N.C N.C N.C N.C N.C N.C Top View 5 FLASH MEMORY ...
Page 6
... K9F2G08R0A K9F2G08U0A PACKAGE DEMENSIONS(FBGA) Top View 10.00 ±0.10 #A1 0.10MAX FLASH MEMORY Bottom View 10.00 ±0.10 0. 7.20 0. 4.00 0. (Datum (Datum 63-∅0.45 ±0.05 ∅ 0. 2.00 Side View 13.00 ±0.10 0.45 ±0.05 6 #A1 INDEX MARK(OPTIONAL ...
Page 7
... K9F2G08R0A K9F2G08U0A PIN CONFIGURATION (ULGA / CLE PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00±0.10 #A1 K9F2G08U0A-ICB0/IIB0 / Vcc NC Vss IO7 IO5 Vcc R/B NC IO6 IO4 IO0 /WE IO2 Vss NC Vss NC Vss /WP IO1 IO3 ALE 2.00 1. 1.00 (Datum (Datum 12-∅1.00±0.05 ∅ 0.1 Side View 17.00 ± ...
Page 8
... K9F2G08R0A K9F2G08U0A PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
Page 9
... K9F2G08R0A K9F2G08U0A Figure 1. K9F2G08X0A Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2. K9F2G08X0A Array Organization 128K Pages (=2,048 Blocks) 2K Bytes Page Register 2K Bytes I/O 0 I/O 1 1st Cycle ...
Page 10
... K9F2G08R0A K9F2G08U0A Product Introduction The K9F2G08X0A is a 2,112Mbit(2,214,592,512 bit) memory organized as 131,072 rows(pages) by 2,112x8 columns. Spare 64x8 columns are located from column address of 2,048~2,111. A 2,112-byte data register is connected to memory cell arrays accommo- dating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made cells that are serially connected to form a NAND structure ...
Page 11
... IH Input Low Voltage, All inputs V (1) IL K9F2G08R0A: I Output High Voltage Level V OH K9F2G08U0A: I K9F2G08R0A: I Output Low Voltage Level V OL K9F2G08U0A: I Output Low Current(R/B) I (R/ NOTE : 1. V can undershoot to -0.4V and V can overshoot Typical value is measured at Vcc=3.3V, T Symbol 1.8V V -0.6 to +2.45 ...
Page 12
... Data Input H X Data Output During Read(Busy During Program(Busy During Erase(Busy Write Protect X X 0V/V Stand-by ( FLASH MEMORY Max Unit 2,048 Blocks K9F2G08U0A 0V to Vcc 5ns Vcc/2 1 TTL GATE and CL=50pF Max Unit Mode Command Input Address Input(5clock) Command Input Address Input(5clock) ...
Page 13
... K9F2G08R0A K9F2G08U0A Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles Block Erase Time NOTE : 1. Typical value is measured at Vcc=3.3V Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25 ...
Page 14
... K9F2G08R0A K9F2G08U0A AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z CE High to ALE or CLE Don’t Care ...
Page 15
... K9F2G08R0A K9F2G08U0A NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
Page 16
... K9F2G08R0A K9F2G08U0A NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
Page 17
... K9F2G08R0A K9F2G08U0A NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
Page 18
... K9F2G08R0A K9F2G08U0A NAND Flash Technical Notes Copy-Back Operation with EDC & Sector Definition for EDC Generally, copy-back program is very powerful to move data stored in a page without utilizing any external memory. But, if the source page has one bit error due to charge loss or charge gain, then without EDC, the copy-back program operation could also accumulate bit errors ...
Page 19
... K9F2G08R0A K9F2G08U0A System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ ...
Page 20
... K9F2G08R0A K9F2G08U0A NOTE I/O Device I/Ox K9F2G08X0A I I/O 7 Command Latch Cycle CLE CE WE ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE t DS I/Ox Col. Add1 DATA Data In/Out Col. Add1 Col. Add2 2,112byte A0~A7 A8~A11 t t CLS CLH ALS ALH ...
Page 21
... K9F2G08R0A K9F2G08U0A Input Data Latch Cycle CLE ALE t ALS I/Ox DIN 0 * Serial Access Cycle after Read I/ R/B NOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. ...
Page 22
... K9F2G08R0A K9F2G08U0A Serial Access Cycle after Read REH RE t REA t CEA I/ R/B NOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. ...
Page 23
... K9F2G08R0A K9F2G08U0A Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Row Add1 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B t CLR 30h Row Add2 Row Add3 Row Address ...
Page 24
... K9F2G08R0A K9F2G08U0A FLASH MEMORY 24 ...
Page 25
... K9F2G08R0A K9F2G08U0A Page Program Operation CLE ALE RE I/Ox 80h Co.l Add1 Col. Add2 Row Add1 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ADL Din Din ...
Page 26
... K9F2G08R0A K9F2G08U0A FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 26 ≈ ...
Page 27
... K9F2G08R0A K9F2G08U0A FLASH MEMORY ≈ ≈ ≈ ≈ 27 ...
Page 28
... K9F2G08R0A K9F2G08U0A Block Erase Operation CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 Row Address R/B Auto Block Erase Setup Command t t BERS WB D0h Busy Erase Command 28 FLASH MEMORY t WHR 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase ...
Page 29
... K9F2G08R0A K9F2G08U0A ≈ ≈ FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 29 ...
Page 30
... K9F2G08R0A K9F2G08U0A FLASH MEMORY 30 ...
Page 31
... K9F2G08R0A K9F2G08U0A Read ID Operation CLE CE WE ALE RE I/Ox 90h Read ID Command Address 1cycle Device Device Code (2nd Cycle) K9F2G08R0A AAh K9F2G08U0A DAh REA Device 00h ECh Code Maker Code Device Code 3rd Cycle 00h 10h 31 FLASH MEMORY 3rd cyc. 4th cyc. ...
Page 32
... K9F2G08R0A K9F2G08U0A ID Definition Table Access command = 90H Description 1 st Byte Maker Code 2 Byte nd Device Code 3 Byte Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc rd 4 Byte Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum th Plane Number, Plane Size ...
Page 33
... K9F2G08R0A K9F2G08U0A 5th ID Data Description 1 2 Plane Number 4 8 64Mb 128Mb 256Mb Plane Size 512Mb (w/o redundant Area) 1Gb 2Gb 4Gb 8Gb Reserved FLASH MEMORY I/O7 I/O6 I/O5 I/O4 I/O3 I/ I/O1 I/ ...
Page 34
... K9F2G08R0A K9F2G08U0A Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 25µ ...
Page 35
... K9F2G08R0A K9F2G08U0A Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 5Cycles Col. Add.1,2 & Row Add.1,2,3 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page ...
Page 36
... K9F2G08R0A K9F2G08U0A Figure 9. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add1,2,3 Data Note: 1. For EDC operation, only one time random data input is possible at the same address. Copy-Back Program The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. ...
Page 37
... K9F2G08R0A K9F2G08U0A EDC OPERATION Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address. Figure 12. Page Copy-Back Program Operation with EDC & ...
Page 38
... K9F2G08R0A K9F2G08U0A Figure 14. Two-Plane Page Program R/B I 80h Address & Data Input Valid Fixed ’Low’ Fixed ’Low’ Fixed ’Low’ NOTE : noticeable that same row address except for A 2. Any command between 11h and 81h is prohibited except 70h and FFh. ...
Page 39
... K9F2G08R0A K9F2G08U0A Two-Plane Copy-Back Program Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous program- ming of two pages. ...
Page 40
... K9F2G08R0A K9F2G08U0A Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input R/B I/Ox Add.(5Cycles) 00h 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0 R/B I/Ox Add.(5Cycles) 85h Col. Add.1,2 & Row Add.1,2,3 1 Destination Address Valid Fixed ’Low’ ...
Page 41
... K9F2G08R0A K9F2G08U0A READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
Page 42
... Device Device Code (2nd Cycle) K9F2G08R0A AAh K9F2G08U0A DAh RESET The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during random read, program or erase mode, the reset operation will abort these operations. The contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased ...
Page 43
... K9F2G08R0A K9F2G08U0A READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
Page 44
... K9F2G08R0A K9F2G08U0A Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 1.1V(1.8V device), 2V(3.3V device). WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum 100µs is required before internal cir- IL cuit gets ready for any command sequences as shown in Figure 21 ...