IDT74LVC163APY Integrated Device Technology, Inc., IDT74LVC163APY Datasheet

IDT74LVC163APY

Manufacturer Part Number

IDT74LVC163APY

Description

3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER WITH SYNCHRONOUS RESET, 5 VOLT TOLERANT I/O

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT74LVC163APY.pdf (7 pages)

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FEATURES:

• 0.5 MICRON CMOS Technology

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

• V

• CMOS power levels (0.4µ µ µ µ µ W typ. static)

• Rail-to-Rail output swing for increased noise margin

• All inputs, outputs, and I/Os are 5V tolerant

• Supports hot insertion

• Available in QSOP, SOIC, SSOP, and TSSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

FUNCTIONAL DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

DESCRIPTION:

features an internal look-ahead carry and can be used for high-speed

counting. Synchronous operation is provided by having all the flip-flops

clocked simultaniously on the positive-going edge of the clock (CP).

IDT74LVC163A

3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER

machine model (C = 200pF, R = 0)

The LVC163A is a synchronous presettable binary counter, which

= 3.3V ± 0.3V, Normal Range

= 2.7V to 3.6V, Extended Range

CET

CEP

BINARY COUNTER

PARALLEL LOAD

CIRCUITRY

3.3V CMOS PRESETTABLE

SYNCHRONOUS 4-BIT BINARY

COUNTER WITH SYNCHRONOUS

RESET, 5 VOLT TOLERANT I/O

Outputs (Q

parallel enable input (PE) disables the counting action and causes the data

at the data inputs (D

edge of the clock (provided that the set-up and hold time requirements for

PE are met). Preset takes place regardless of the levels at count enable

inputs (CEP and CET). A low level at the master reset input (MR) sets all

four outputs of the flip-flops (Q

transition on the clock (CP) input (provided that the set-up and hold time

requirements for PE are met).

inputs. This synchronous reset feature enables the designer to modify the

maximum count with only one external NAND gate.

count enable inputs (CEP and CET) must be high to count. The CET input

is fed forward to enable the terminal count output (TC). The TC output thus

enabled will produce a high output pulse of a duration approximately equal

to a high level output of Q

cascaded stage. The maximum clock frequency for the cascaded counters

is determined by the CP to TC propagation delay and CEP to CP set-up

time, according to the following formula:

STATE DIAGRAM

This action occurs regardless of the levels of CP, PE, CET, and CEP

The look-ahead carry simplifies serial cascading of the counters. Both

max

to Q

) may be preset to a high or low level. A low level at the

(max)

to D

(CP to TC) + t

) to be loaded into the counter on the positive-going

. This pulse can be used to enable the next

to Q

INDUSTRIAL TEMPERATURE RANGE

) to low level after the next positive-going

(CEP to CP)

IDT74LVC163A

OCTOBER 1999

DSC-4949/1

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IDT74LVC163APY Summary of contents

Page 1

... The IDT logo is a registered trademark of Integrated Device Technology, Inc. INDUSTRIAL TEMPERATURE RANGE ©1999 Integrated Device Technology, Inc. 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER WITH SYNCHRONOUS RESET, 5 VOLT TOLERANT I/O Outputs (Q parallel enable input (PE) disables the counting action and causes the data ...

Page 2

IDT74LVC163A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER FUNCTIONAL BLOCK DIAGRAM D0 CET CEP FF0 FF1 INDUSTRIAL TEMPERATURE RANGE D3 FF2 FF3 D Q ...

Page 3

IDT74LVC163A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER TYPICAL TIMING SEQUENCE CEP CET RESET PRESET COUNT PIN CONFIGURATION ...

Page 4

IDT74LVC163A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER FUNCTION TABLE (1) OPERATING MODES MR CP ↑ Reset (clear) l ↑ Parallel load h ↑ h ↑ Count h Hold h X (do nothing NOTE HIGH ...

Page 5

IDT74LVC163A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER OUTPUT DRIVE CHARACTERISTICS Symbol Parameter V Output HIGH Voltage OH V Output LOW Voltage OL NOTE and V must be within the min. or max. range shown in the DC ...

Page 6

IDT74LVC163A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER TEST CIRCUITS AND WAVEFORMS TEST CONDITIONS (1) Symbol V = 2.5V±0. Vcc LOAD V Vcc IH V Vcc / 150 LZ V 150 ...

Page 7

IDT74LVC163A 3.3V CMOS PRESETTABLE SYNCHRONOUS 4-BIT BINARY COUNTER ORDERING INFORMATION XX LVC XXXX IDT Temp. Range Device Type CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 XX Package Q Quarter Size Outline Package DC Small Outline IC PY Shrink ...

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