XC68HC705JB3JP Motorola, XC68HC705JB3JP Datasheet
XC68HC705JB3JP
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... Motorola does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical ...
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... Carry/Borrow Bit (C-Bit) ............................................................................... 3-4 4.1 INTERRUPT VECTORS .................................................................................. 4-1 4.2 INTERRUPT PROCESSING............................................................................ 4-2 4.3 RESET INTERRUPT SEQUENCE .................................................................. 4-4 4.4 SOFTWARE INTERRUPT (SWI) ..................................................................... 4-4 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 1 GENERAL DESCRIPTION SECTION 2 MEMORY SECTION 3 CENTRAL PROCESSING UNIT SECTION 4 INTERRUPTS Page MOTOROLA i ...
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... PB1, PB2 Slow Transition Output................................................................ 7-4 7.3 PORT-C ........................................................................................................... 7-5 7.3.1 Port-C Data Register ................................................................................... 7-5 7.3.2 Port-C Data Direction Register .................................................................... 7-5 7.3.3 Port-C Pull-down/up Register ...................................................................... 7-6 MOTOROLA ii November 5, 1998 TABLE OF CONTENTS SECTION 5 RESETS SECTION 6 LOW POWER MODES SECTION 7 INPUT/OUTPUT PORTS Page ...
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... USB Interrupt Register 1 (UIR1) .............................................................. 10-21 10.5.4 USB Control Register 0 (UCR0) .............................................................. 10-22 10.5.5 USB Control Register 1 (UCR1) .............................................................. 10-23 10.5.6 USB Control Register 2 (UCR2) .............................................................. 10-24 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 8 MULTI-FUNCTION TIMER SECTION 9 16-BIT TIMER SECTION 10 Page MOTOROLA iii ...
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... MAXIMUM RATINGS..................................................................................... 13-1 13.2 THERMAL CHARACTERISTICS ................................................................... 13-1 13.3 DC ELECTRICAL CHARACTERISTICS........................................................ 13-2 13.4 USB DC ELECTRICAL CHARACTERISTICS ............................................... 13-3 13.5 USB LOW SPEED SOURCE ELECTRICAL CHARACTERISTICS............... 13-4 13.6 CONTROL TIMING ........................................................................................ 13-5 MOTOROLA iv November 5, 1998 TABLE OF CONTENTS SECTION 11 OPTICAL INTERFACE SECTION 12 INSTRUCTION SET SECTION 13 Page MC68HC05JB3 ...
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... MASK OPTION REGISTER (MOR) .................................................................A-1 A.4 BOOTSTRAP MODE .......................................................................................A-3 A.5 EPROM PROGRAMMING ...............................................................................A-3 A.5.1 EPROM Program Control Register (PCR)...................................................A-3 A.5.2 Programming Sequence ..............................................................................A-4 A.6 EPROM PROGRAMMING SPECIFICATIONS ................................................A-5 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION TABLE OF CONTENTS SECTION 14 APPENDIX A MC68HC705JB3 Page MOTOROLA v ...
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... GENERAL RELEASE SPECIFICATION Section MOTOROLA vi November 5, 1998 TABLE OF CONTENTS Page MC68HC05JB3 REV 1 ...
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... CRC Block Diagram for Address and Endpoint Fields................................... 10-6 10-7 CRC Block Diagram for Data Packets ........................................................... 10-7 10-8 EOP Transaction Voltage Levels ................................................................... 10-8 10-9 EOP Width Timing.......................................................................................... 10-8 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION LIST OF FIGURES Title Page MOTOROLA vii ...
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... PDIP Mechanical Dimensions ............................................................ 14-1 14-2 28-Pin PDIP Mechanical Dimensions ............................................................ 14-1 14-3 20-Pin SOIC Mechanical Dimensions ............................................................ 14-2 14-4 28-Pin SOIC Mechanical Dimensions ............................................................ 14-2 A-1 MC68HC705JB3 Memory Map ........................................................................A-2 A-2 EPROM Programming Sequence ....................................................................A-5 MOTOROLA viii November 5, 1998 LIST OF FIGURES Title Page MC68HC05JB3 REV 1 ...
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... DC Electrical Characteristics.......................................................................... 13-2 13-2 USB DC Electrical Characteristics ................................................................. 13-3 13-3 USB Low Speed Source Electrical Characteristics ........................................ 13-4 13-4 Control Timing................................................................................................ 13-5 A-1 EPROM Programming Electrical Characteristics .............................................A-5 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION LIST OF TABLES Title =3.0MHz................................................................ 8-3 OP Page MOTOROLA ix ...
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... GENERAL RELEASE SPECIFICATION Table MOTOROLA x November 5, 1998 LIST OF TABLES Title Page MC68HC05JB3 REV 1 ...
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... Multi-Function Timer (MFT) • 16-bit Timer with 1 input capture and 1 output compare • Low Voltage Reset (LVR) • Computer Operating Properly (COP) Watchdog Reset • Illegal Address Reset MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 1 GENERAL DESCRIPTION GENERAL DESCRIPTION MOTOROLA 1-1 ...
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... OSC, crystal/ceramic resonator startup delay: [4064 or 224 internal bus cycles] • Low Voltage Reset (LVR): [enabled or disabled] • COP function of MFT: [enabled or disabled] 1.3 MCU STRUCTURE Figure 1-1 shows the structure of MC68HC05JB3 MCU. MOTOROLA 1-2 November 5, 1998 GENERAL DESCRIPTION MC68HC05JB3 REV 1 ...
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... O/P : Pins available in 28-pin package only † : PC0 shared with OCMP GENERAL DESCRIPTION VDD LVR POWER VSS VREF SUPPLY 3.3V RESET RESET and IRQ IRQ OSC1 Core OSC TImer 2 OSC2 TCAP 16-bit Timer † OCMP Low Speed D+ USB D– MOTOROLA 1-3 ...
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... The OSC1 and OSC2 pins are the connections for the on-chip oscillator. The OSC1 and OSC2 pins can accept the following sets of components crystal as shown in Figure 1-3 ( ceramic resonator as shown in Figure 1-3 ( external clock signal as shown in Figure 1-3 (b) MOTOROLA 1-4 November 5, 1998 20 VDD ...
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... M is provided between OSC1 and OSC2 for the ceramic resonator type oscillator as a mask option. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION . If the internal operating frequency is OP resistor may be selected between OSC1 (b) External Clock Source Connection GENERAL DESCRIPTION MCU OSC2 Unconnected External Clock MOTOROLA 1-5 ...
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... PA0-PA7 These eight I/O lines comprise Port A. PA0 to PA7 are push-pull pins with pull- down devices. The state of any pin is software programmable and all Port A lines are configured as inputs during power-on or reset. MOTOROLA 1-6 November 5, 1998 DD for "wired-OR" operation, if desired. The IRQ pin contains ...
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... PC0 to PC3 are push-pull pins with pull-down devices. PC0 is also shared with the OCMP pin from the output compare function of the 16-bit timer. Port C is only available in the 28-pin package. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION GENERAL DESCRIPTION MOTOROLA 1-7 ...
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... GENERAL RELEASE SPECIFICATION MOTOROLA 1-8 November 5, 1998 GENERAL DESCRIPTION MC68HC05JB3 REV 1 ...
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... IRQ Vector (Low Byte) SWI Vector (High Byte) SWI Vector (Low Byte) Reset Vector (High Byte) Reset Vector (Low Byte) MEMORY $0000 $003F $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF MOTOROLA 2-1 ...
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... There are a total of 3k-bytes of ROM on chip. This includes 2560 bytes of user ROM with locations $1400 to $1DFF for user program storage and 16 bytes for user vectors at locations $1FF0 to $1FFF. Also, 496 bytes of Self-check ROM on chip at locations $1E00 to $1FEF. MOTOROLA 2-2 November 5, 1998 MEMORY ...
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... BIT 0 PA3 PA2 PA1 PA0 PB2 PB1 PB0 PC3 PC2 PC1 PC0 DDRC3 DDRC2 DDRC1 DDRC0 0 0 RT1 RT0 TOFR RTIFR TMR3 TMR2 TMR1 TMR0 IRQF 0 0 IRQPU IRQR OIE3 OIE2 OIE1 OIE0 PDRC3 PDRC2 PDRC1 PDRC0 reserved bits MOTOROLA 2-3 ...
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... ACNTL W R $001C Unused W R $001D Unused W R $001E Unused W R $001F Unused W Figure 2-3. MC68HC05JB3 I/O Registers $0010-$001F MOTOROLA 2-4 November 5, 1998 BIT 7 BIT 6 BIT 5 BIT 4 PDRA7 PDRA6 PDRA5 PDRA4 PDRB7 PDRB6 PDRB5 PDRB4 0 ICIE OCIE TOIE ICF ...
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... UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 UE1TD7 UE1TD6 UE1TD5 UE1TD4 UE1TD3 UE1TD2 UE1TD1 UE1TD0 unused bits MEMORY BIT 3 BIT 2 BIT 1 BIT 0 reserved bits MOTOROLA 2-5 ...
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... Reserved W Figure 2-5. MC68HC05JB3 I/O Registers $0030-$003F ADDR REGISTER R/W COP Register R $1FF0 COPR W Figure 2-6. COP Register (COPR) MOTOROLA 2-6 November 5, 1998 BIT 7 BIT 6 BIT 5 BIT 4 0 TX1ST 0 TX1STR USBEN UADD6 UADD5 UADD4 UADD3 UADD2 UADD1 UADD0 TXD0F ...
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... CONDITION CODE REGISTER Figure 3-1. MC68HC05 Programming Model MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION ACCUMULATOR INDEX REGISTER STACK POINTER PROGRAM COUNTER HALF-CARRY BIT (FROM BIT 3) INTERRUPT MASK NEGATIVE BIT ZERO BIT CARRY BIT CENTRAL PROCESSING UNIT MOTOROLA 3-1 ...
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... The program counter shown in Figure 3 16-bit register. In MCU devices with memory space less than 64k-bytes the unimplemented upper address lines are ignored. The program counter contains the address of the next instruction or operand to be fetched. MOTOROLA 3-2 November 5, 1998 CENTRAL PROCESSING UNIT ...
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... Zero Bit (Z-Bit) The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation, or data load operation was zero. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION CENTRAL PROCESSING UNIT MOTOROLA 3-3 ...
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... The carry/borrow bit is also set or cleared during bit test and branch instructions and during shifts and rotates. This bit is neither set by an INC nor by a DEC instruction. MOTOROLA 3-4 November 5, 1998 CENTRAL PROCESSING UNIT ...
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... CTOFE Bit — I Bit RTIE Bit Reserved Reserved INTERRUPTS Priority Vector (1 = Highest) Address 1 $1FFE–$1FFF Same Priority $1FFC–$1FFD As Instruction 2 $1FFA–$1FFB 3 $1FF8–$1FF9 4 $1FF6–$1FF7 5 $1FF4–$1FF5 $1FF2–$1FF3 $1FF0–$1FF1 MOTOROLA 4-1 ...
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... CONDITION CODE REGISTER n+1 n+2 n+3 PROGRAM COUNTER (HIGH BYTE) n+4 PROGRAM COUNTER (LOW BYTE) $00FD $00FE $00FF Figure 4-1. Interrupt Stacking Order MOTOROLA 4-2 November 5, 1998 NOTE (BOTTOM OF RAM) (BOTTOM OF STACK) ACCUMULATOR INDEX REGISTER STACKING ORDER TOP OF STACK (RAM) INTERRUPTS ...
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... RTI INSTRUCTION? MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION YES CLEAR IRQ LATCH. NO YES NO YES NO YES NO STACK PCL, PCH CCR. SET I BIT. LOAD PC WITH INTERRUPT VECTOR. YES NO YES UNSTACK CCR PCH, PCL. NO EXECUTE INSTRUCTION. Figure 4-2. Interrupt Flowchart INTERRUPTS MOTOROLA 4-3 ...
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... Low level on the IRQ pin. 2. Falling edge on the IRQ pin. 3. Low level on any PA0-PA3 pin with IRQ enabled (via mask option). 4. Falling edge on any PA0-PA3 pin with IRQ enabled (via mask option). MOTOROLA 4-4 November 5, 1998 INTERRUPTS MC68HC05JB3 ...
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... November 5, 1998 GENERAL RELEASE SPECIFICATION V DD IRQ LATCH R IRQ Level RST IRQ VECTOR FETCH IRQ STATUS/CONTROL REGISTER INTERNAL DATA BUS BIT 6 BIT 5 BIT INTERRUPTS TO BIH & BIL INSTRUCTION PROCESSING EXTERNAL INTERRUPT REQUEST BIT 3 BIT 2 BIT 1 BIT 0 IRQF 0 0 IRQPU IRQR MOTOROLA 0 4-5 ...
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... IRQ pin. This mask option of PA0-3 interrupt allow all of these input pins to be OR’ed with the input present on the IRQ pin. All PA0 to PA3 pins must be selected as a group as an additional IRQ interrupt. All the PA0-3 interrupt sources are also controlled by the IRQE enable bit. MOTOROLA 4-6 November 5, 1998 INTERRUPTS ...
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... The MFT interrupt is generated by the MFT module as described in the section on Multi-function Timer. These interrupts will vector to the same interrupt service rou- tine located at the address specified by the contents of memory locations $1FF4 and $1FF5. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION NOTE NOTE INTERRUPTS MOTOROLA 4-7 ...
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... GENERAL RELEASE SPECIFICATION MOTOROLA 4-8 November 5, 1998 INTERRUPTS MC68HC05JB3 REV 1 ...
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... USB RESET DETECTION COP WATCHDOG LOW VOLTAGE RESET V POWER-ON RESET DD ILLEGAL ADDRESS RESET RESET MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 5 RESETS INTERNAL ADDRESS BUS Figure 5-1. Reset Sources RESETS S TO CPU RST D AND RESET SUBSYSTEMS LATCH R INTERNAL CLOCK MOTOROLA 5-1 ...
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... The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 224 or 4064 (224 or 4064 is selected by mask option) internal processor bus clock cycles after the oscillator becomes active. MOTOROLA 5-2 November 5, 1998 pin generates a power-on reset. The power-on ...
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... RESET pin low one cycle of the internal bus clock. The Low Volt- age Reset circuit is enabled by a mask option. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 BIT RESETS must drop BIT 2 BIT 1 BIT COPC MOTOROLA 5-3 ...
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... Illegal Address Reset An opcode fetch from an address that is not in the ROM or the RAM generates an illegal address reset. The illegal address reset will assert the pull-down device to pull the RESET pin low for cycles of the internal bus clock. MOTOROLA 5-4 November 5, 1998 RESETS ...
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... There are three modes of operation that reduce power consumption: • Stop mode • Wait mode • Data retention mode Figure 6-1 shows the sequence of events in Stop and Wait modes. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 6 LOW POWER MODES LOW POWER MODES MOTOROLA 6-1 ...
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... DELAY? RESTART INTERNAL PROCESSOR CLOCK 1. LOAD PC WITH RESET VECTOR 2. SERVICE INTERRUPT. a. SAVE CPU REGISTERS ON STACK. b. SET I BIT IN CCR. c. LOAD PC WITH INTERRUPT VECTOR. Figure 6-1. STOP and WAIT Flowchart MOTOROLA 6-2 November 5, 1998 YES NO OR LOW POWER MODES WAIT EXTERNAL OSCILLATOR ACTIVE, ...
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... The data retention feature allows the MCU DD to remain in a low power consumption state during which it retains data, but the CPU cannot execute instructions. The RESET pin must be held low during data- retention mode. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION LOW POWER MODES MOTOROLA 6-3 ...
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... GENERAL RELEASE SPECIFICATION MOTOROLA 6-4 November 5, 1998 LOW POWER MODES MC68HC05JB3 REV 1 ...
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... GENERAL RELEASE SPECIFICATION SECTION 7 INPUT/OUTPUT PORTS Current Drive/Sink 1.6mA sink External Interrupt 1 8mA sink 1.6mA sink shared with TCAP 25mA sink, 1 open-drain 1 1.6mA sink shared with OCMP INPUT/OUTPUT PORTS Additional Features 2 Optical Interface Slow Transition Output Pins available only in 28-pin device MOTOROLA 7-1 ...
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... Internal pull-down enabled. 7.1.4 PA0-PA3 Interrupts A mask option selects the capability for PA0-PA3 to be used as external IRQ inter- rupt inputs. These four I/O pins also have schmitt trigger input circuits. See INTERRUPTS section for detail. MOTOROLA 7-2 November 5, 1998 DDRAx Pin Configuration ...
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... PB0, PB4-PB7: Output Push-Pull 1 PB1, PB2: Output Open-drain BIT 6 BIT 5 BIT 4 PB6 PB5 PB4 BIT 6 BIT 5 BIT 4 DDRB6 DDRB5 DDRB4 SLOWE INPUT/OUTPUT PORTS Input BIT 3 BIT 2 BIT 1 BIT 0 0 PB2 PB1 PB0 BIT 3 BIT 2 BIT 1 BIT 0 DDRB2 DDRB1 DDRB0 MOTOROLA 0 0 7-3 ...
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... PB1 — a high-to-low output transition is a slow falling edge (drops from 5.0V to 2.2V in 167ns typically The fast transition duration is depending on the strength of the output SS driver defined for each port. See Figure 7-1. Both PB1 and PB2 have 25mA current sink capability. MOTOROLA 7-4 November 5, 1998 BIT 6 BIT 5 BIT 4 PDRB6 ...
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... DDRCx Pin Configuration 0 Input with pull-down 1 Output Push-Pull 0 1 Output Push-Pull BIT 6 BIT 5 BIT BIT 6 BIT 5 BIT 4 VROFF DDRC3 INPUT/OUTPUT PORTS 330ns Input BIT 3 BIT 2 BIT 1 BIT 0 PC3 PC2 PC1 PC0 BIT 3 BIT 2 BIT 1 BIT 0 DDRC2 DDRC1 DDRC0 MOTOROLA 0 0 7-5 ...
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... Port-C pull-down/up control register (PDURC) at location $000F. BIT 7 PDURC R $000F W reset: 0 PDRCx — PCx Pin Pull-down Enable 1 = Internal pull-down disabled Internal pull-down enabled. MOTOROLA 7-6 November 5, 1998 BIT 6 BIT 5 BIT 4 BIT 3 PDRC3 INPUT/OUTPUT PORTS ...
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... Figure 8-1. Multi-Function Timer Block Diagram MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 8 MULTI-FUNCTION TIMER MCU Internal Bus 7-bit counter ÷2 ÷2 ÷2 CTOFR RTIFR RT1 RT0 MULTI-FUNCTION TIMER 2 f ÷2 Internal OP ÷4 Timer Clock (NTF1) COP Watchdog Resetable Timer (÷8) MOTOROLA 8-1 ...
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... OP capture. Extended time periods can be attained using the CTOF function to incre- ment a temporary RAM storage location thereby simulating a 16-bit (or more) counter. The value of each bit of the TCNT is shown in Figure 8-2. This register is cleared by reset. MOTOROLA 8-2 November 5, 1998 MULTI-FUNCTION TIMER ÷ ...
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... Bus Frequency, f Divide Ratio RTI Rate 14 2 5.46ms 15 2 10.92ms 16 2 21.85ms 17 2 43.69ms MULTI-FUNCTION TIMER BIT 2 BIT 1 BIT 0 TMR2 TMR1 TMR0 BIT 2 BIT 1 BIT RT1 RT0 RTIFR =3.0MHz =f =3.0 MHz BUS OP COP Reset Period (RTI 8) 43.68ms 87.36ms 174.8ms 349.52ms MOTOROLA 8-3 ...
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... COP CONSIDERATION DURING STOP MODE In STOP mode, the clock to the Watchdog Timer is stopped and is therefore impossible to generate COP reset when in STOP mode. The COP function will resume 224 or 4064 cycles after exiting from STOP. MOTOROLA 8-4 November 5, 1998 MULTI-FUNCTION TIMER MC68HC05JB3 ...
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... ICRH ($0014) ICRL ($0015) TMRH ($0018) TMRL ($0019) 16-BIT COUNTER 16-BIT COMPARATOR OCRH ($0016) OCRL ($0017) TIMER STATUS REGISTER 16-BIT TIMER ACRH ($001A) ACRL ($001B) INTERNAL 4 CLOCK (f 2) OSC PORT-C LOGIC PC0/ MUX OCMP OCMPO TIMER INTERRUPT REQUEST $0013 MOTOROLA 9-1 ...
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... LSB of the 16-bit timer counter. READ READ TMRH ($FFFC) RESET TIMER CONTROL REG. $0012 Figure 9-2. Programmable Timer Counter Block Diagram MOTOROLA 9-2 November 5, 1998 LATCH TMRL ($0019) TMRH ($0018) TMR LSB 16-BIT COUNTER OVERFLOW (TOF) TIMER STATUS REG. ...
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... I bit in the condition code register (CCR) before reading TMRH and clear the I bit after reading TMRL. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 TMRH6 TMRH5 TMRH4 TMRH3 TMRL6 TMRL5 TMRL4 TMRL3 NOTE 16-BIT TIMER BIT 3 BIT 2 BIT 1 BIT 0 TMRH2 TMRH1 TMRH0 TMRL2 TMRL1 TMRL0 MOTOROLA 1 0 9-3 ...
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... Reading the ACRH and ACRL in any order or any number of times does not have any effect on the 16-bit free-running counter or the TOF flag bit. MOTOROLA 9-4 November 5, 1998 LATCH ...
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... GENERAL RELEASE SPECIFICATION NOTE ICRH ($0014) ICRL ($0015) LATCH 16-BIT COUNTER INPUT CAPTURE (ICF) TIMER CONTROL REG. TIMER STATUS REG. NOTE /2 reference voltage. DD 16-BIT TIMER INTERNAL DATA BUS READ ICRL INTERNAL 4 CLOCK (f 2) OSC TIMER INTERRUPT REQUEST $0013 INTERNAL DATA BUS MOTOROLA 9-5 ...
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... Figure 9-8. Switching off the V DD power when the MCU low power mode. PB0/ TCAP Voltage Reference REF EN Figure 9-7. TCAP Input Signal Conditioning MOTOROLA 9-6 November 5, 1998 BIT 6 BIT 5 BIT 4 BIT 3 VREF2 VREF1 VREF0 NOTE /2 reference are enabled, PB0 pin will automatically ...
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... Figure 9-9. Input Capture Registers (ICRH, ICRL) MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION Output of Comparator Signal on TCAP pin Time BIT 6 BIT 5 BIT 4 BIT 3 ICRH6 ICRH5 ICRH4 ICRH3 ICRL6 ICRL5 ICRL4 ICRL3 16-BIT TIMER BIT 2 BIT 1 BIT 0 ICRH2 ICRH1 ICRH0 ICRL2 ICRL1 ICRL0 MOTOROLA 9-7 ...
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... Writing to the OCRH before writing to the OCRL inhibits timer compares until the OCRL is written. Reading or writing to the OCRL after reading the TSR will clear the output compare flag bit (OCF). MOTOROLA 9-8 November 5, 1998 NOTE ...
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... OCRH5 OCRH4 OCRH3 OCRL6 OCRL5 OCRL4 OCRL3 16-BIT TIMER PORT-C LOGIC OCMPO (bit7 at $06) MUX OCMP INTERNAL 4 CLOCK (f OSC TIMER INTERRUPT REQUEST R/W OCRL $0013 INTERNAL DATA BUS BIT 3 BIT 2 BIT 1 BIT 0 OCRH2 OCRH1 OCRH0 OCRL2 OCRL1 OCRL0 MOTOROLA PC0 9-9 ...
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... Output compare interrupts disabled. TOIE - TIMER OVERFLOW INTERRUPT ENABLE This read/write bit enables interrupts caused by a timer overflow. Reset clears the TOIE bit Timer overflow interrupts enabled Timer overflow interrupts disabled. MOTOROLA 9-10 November 5, 1998 DISABLE INTERRUPTS ..... ..... ...
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... Clear the TOF bit by reading the timer status register with the TOF set, and then accessing the low byte (TMRL, $0019) of the timer registers. Reset has no effect on TOF. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 BIT 3 OCF TOF 16-BIT TIMER BIT 2 BIT 1 BIT MOTOROLA 9-11 ...
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... If the STOP mode is exited by an external reset, no input capture flag or data will be present even if a valid input capture edge was detected during the STOP mode. MOTOROLA 9-12 November 5, 1998 16-BIT TIMER ...
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... Suspend and resume operations • Remote Wake-up support • USB generated interrupts • Transaction interrupt driven • Resume interrupt • End of Packet interrupt • STALL, NAK, and ACK handshake generation MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 10 UNIVERSAL SERIAL BUS MODULE MOTOROLA 10-1 ...
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... These blocks consist of a 3.3 volt regulator, a dual function transceiver, the USB control logic, and the endpoint registers. The blocks are further detailed in Section 10.4. CPU BUS Figure 10-1. USB Block Diagram MOTOROLA 10-2 November 5, 1998 RCV VPIN ...
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... OUT DATA1 ACK IN DATA1 ACK OUT IN DATA1 ACK ACK UNIVERSAL SERIAL BUS MODULE types supported by ACK OUT DATA0/1 ACK IN DATA1 ACK ACK IN DATA0/1 ACK DATA1 ACK ACK KEY: Unrelated Bus Traffic Host Generated Device Generated MOTOROLA the 10-3 ...
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... This switch in levels represents the first bit of the Sync field. Figure 10-5 shows the data signaling and voltage levels for the start of packet and the sync pattern. MOTOROLA 10-4 November 5, 1998 SYNC ...
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... GENERAL RELEASE SPECIFICATION FIRST BIT OF PACKET PID Value PID Type %1001 IN Token %0001 OUT Token %1101 SETUP Token %0011 DATA0 Packet %1011 DATA1 Packet %0010 ACK Handshake %1010 NAK Handshake %1110 STALL Handshake UNIVERSAL SERIAL BUS MODULE END OF SYNC MOTOROLA 10-5 ...
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... Update every bit time Reset to ones at SOP Data Stream next bit Figure 10-6. CRC Block Diagram for Address and Endpoint Fields MOTOROLA 10-6 November 5, 1998 Generator Polynomial ...
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... The bus termination resistors hold the bus in the idle state. Figure 10-8 shows the data signaling and voltage levels for an end of packet transaction. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION Generator Polynomial MUX 16 16 RECEIVE Good CRC Y UNIVERSAL SERIAL BUS MODULE Expected Residual Equal? Bad CRC N MOTOROLA 10-7 ...
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... Section 9.1 of the USB specification). The device must be able to accept a device address via a SET_ADDRESS command (refer to section 9.4 of the USB specification) no later than 10 ms after the reset is removed. MOTOROLA 10-8 November 5, 1998 LAST BIT OF PACKET ...
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... Hub. A non-idle state (“K” state) on the USB data lines is accomplished by asserting the FRESUM bit in the UCR1 register. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION supply when in the suspend state. This includes the current UNIVERSAL SERIAL BUS MODULE to ground termination resistors MOTOROLA 10-9 ...
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... The USB module as previously shown in Figure 10-1 contains four functional blocks: a 3.3 volt regulator USB transceiver, the USB control logic, and the USB registers. The following will detail the function of the regulator, transceiver and control logic. See Section 10.5 for the register discussion. MOTOROLA 10-10 November 5, 1998 3.3V Regulator Out 1 ...
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... Figure 10-11. Regulator Electrical Connections MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 VROFF DDRC3 VROFF USB Data Lines R1 USB Cable 15K 5% UNIVERSAL SERIAL BUS MODULE BIT 3 BIT 2 BIT 1 BIT 0 DDRC2 DDRC1 DDRC0 Host or Hub R2 R2 MOTOROLA 0 10-11 ...
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... D+ being at least 200 mV more positive than D– as seen at the receiver, and a differential 0 is represented by D– being at least 200 mV more positive than D+ as seen at the receiver. The signal cross over point must be between 1.3V and 2.0V. MOTOROLA 10-12 November 5, 1998 load to 3.6 V and in its high state is above the V load to ground ...
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... The data jitter is PERIOD MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 COMMON MODE INPUT VOLTAGE (VOLTS) time between any UNIVERSAL SERIAL BUS MODULE 2.4 2.6 2.8 3.0 3.2 set of data transitions MOTOROLA 10-13 is ...
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... This same buffer is used for receive transactions to count the number of bytes received and, upon the end of the transaction, transfer that number to the receive endpoints byte count register. MOTOROLA 10-14 November 5, 1998 CROSSOVER ...
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... Figure 10-17. Flow Diagram for NRZI MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION POWER UP NO PACKET IDLE BEGIN PACKET TRANSMISSION FETCH THE DATA BIT IS DATA NO YES BIT = 0? NO DATA TRANSITION TRANSITION DATA IS PACKAGE NO YES TRANSFER DONE? UNIVERSAL SERIAL BUS MODULE MOTOROLA 10-15 ...
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... RAW DATA BIT STUFFED DATA NRZI IDLE ENCODED DATA MOTOROLA 10-16 November 5, 1998 SYNC PATTERN PACKET DATA SYNC PATTERN PACKET DATA SIX ONES SYNC PATTERN PACKET DATA Figure 10-18. Bit Stuffing ...
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... GENERAL RELEASE SPECIFICATION POWER UP NO PACKET IDLE BEGIN PACKET TRANSMISSION RESET BIT COUNTER TO 0 GET NEXT BIT = BIT VALUE? INCREMENT THE COUNTER NO YES COUNTER = 6? INSERT A ZERO BIT RESET THE BIT COUNTER PACKAGE NO YES TRANSFER DONE? UNIVERSAL SERIAL BUS MODULE MOTOROLA 10-17 ...
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... UE0RD7 UE0RD6 UE0RD5 UE0RD4 USB Endpoint 0 Data Register 7 (UE0D7) UE0TD7 UE0TD6 UE0TD5 USB Endpoint 1/2 Data Register 0 (UE1D0) UE1TD7 UE1TD6 UE1TD5 USB Endpoint 1/2 Data Register 7 (UE1D7) UE1TD7 UE1TD6 UE1TD5 MOTOROLA 10-18 November 5, 1998 Table 10-2. Register Summary TX1ST 0 ENABLE2 ENABLE1 STALL2 ...
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... REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 UADD6 UADD5 UADD4 UADD3 BIT 6 BIT 5 BIT 4 RXD0F RSTF SUSPND TXD0IE UNIVERSAL SERIAL BUS MODULE BIT 3 BIT 2 BIT 1 BIT 0 UADD2 UADD1 UADD0 BIT 3 BIT 2 BIT 1 BIT 0 0 RXD0IE TXD0FR RXD0FR MOTOROLA 10-19 ...
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... TXD0FR has no effect. Reset clears this bit. RXD0FR — Endpoint 0 Receive Flag Reset Writing a logic 1 to this write only bit will clear the RXD0F bit set.Writing a logic 0 to RXD0FR has no effect. Reset clears this bit. MOTOROLA 10-20 November 5, 1998 UNIVERSAL SERIAL BUS MODULE ...
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... USB interrupts enabled for Transmit Endpoints 1 and USB interrupts disabled for Transmit Endpoints 1 and 2. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 BIT 3 EOPF RESUMF 0 TXD1IE RESUMFR UNIVERSAL SERIAL BUS MODULE BIT 2 BIT 1 BIT EOPIE TXD1FR EOPFR MOTOROLA 10-21 ...
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... If this bit the TXD0F is set, the USB will respond with a NAK handshake to any Endpoint 0 IN tokens. Reset clears this bit Data is ready to be sent Data is not ready. Respond with NAK. MOTOROLA 10-22 November 5, 1998 BIT 6 BIT 5 BIT 4 ...
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... Endpoint 1, the USB responds with a NAK handshake packet The data buffers are used for Endpoint The data buffers are used for Endpoint 1. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 BIT 3 TX1E FRESUM TP1SZ3 TP1SIZ2 TP1SIZ1 TP1SIZ0 UNIVERSAL SERIAL BUS MODULE BIT 2 BIT 1 BIT MOTOROLA 10-23 ...
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... That is, this bit will be set if an Endpoint 0 Transmit Flag is still set at the end of an Endpoint 0 reception. This bit lets the firmware know that the Endpoint 0 transmission happened before the Endpoint 0 reception. Reset clears this bit transaction occurred before SETUP/OUT transaction occurred after SETUP/OUT. MOTOROLA 10-24 November 5, 1998 BIT 6 BIT 5 BIT 4 ...
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... Last token received for Endpoint 0 was a SETUP token Last token received for Endpoint 0 was not a SETUP token. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 SETUP 0 0 RPSIZ3 UNIVERSAL SERIAL BUS MODULE BIT 3 BIT 2 BIT 1 BIT 0 RPSIZ1 RPSIZ0 RPSIZ2 MOTOROLA U 10-25 ...
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... Endpoints 1 and 2 and depend on proper configuration of the ENDADD bit. 10.6 USB INTERRUPTS The USB module is capable of generating interrupts and causing the CPU to execute the USB interrupt service routine. There are three types of USB interrupts: MOTOROLA 10-26 November 5, 1998 BIT 6 BIT 5 BIT 4 BIT 3 ...
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... UIR1 register. There is no interrupt enable bit for this interrupt source and an interrupt will be executed if the I bit in the CCR is cleared. A resume interrupt can only occur while the MC68HC05JB3 is in the suspend mode. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION UNIVERSAL SERIAL BUS MODULE MOTOROLA 10-27 ...
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... The USB module can generate a USB interrupt upon detection of an end of packet signal (a single ended 0) for low speed devices. Upon detection of an SE0 sequence, the USB module sets the EOPF bit and will generate an interrupt if the EOPIE bit in the UIR1 register is set. MOTOROLA 10-28 November 5, 1998 UNIVERSAL SERIAL BUS MODULE ...
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... Figure 10-29. OUT Token Data Flow for Receive Endpoint 0 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION UNIVERSAL SERIAL BUS MODULE Time-out No Response from USB function No Response from USB function Send STALL Handshake Send NAK Handshake Ignore transaction No response from USB function No Interrupt MOTOROLA 10-29 ...
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... Error free DATA packet? Y Set RXD0F Receive Control Endpoint Interrupt Enabled? (RXD0IE = 1) Y Valid transaction Interrupt generated Figure 10-30. SETUP Token Data Flow for Receive Endpoint 0 MOTOROLA 10-30 November 5, 1998 Clear STALL0 bit N N UNIVERSAL SERIAL BUS MODULE No Response from USB function ...
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... Valid transaction Interrupt generated Figure 10-31. IN Token Data Flow for Transmit Endpoint 0 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION UNIVERSAL SERIAL BUS MODULE No Response from USB function Send STALL Handshake Send NAK Handshake No Response from USB function No Interrupt MOTOROLA 10-31 ...
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... ACK received and no Time-out condition occurs? Y Set TXD1F to 1 Transmit Endpoint Interrupt Enabled? (TXD1IE = 1) Valid transaction Interrupt generated Figure 10-32. IN Token Data Flow for Transmit Endpoint 1/2 MOTOROLA 10-32 November 5, 1998 UNIVERSAL SERIAL BUS MODULE No Response from USB function Send STALL ...
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... IR displacement encoders. The reference voltage is selected using the bits VREF0-VREF2 in the OIER. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 11 OPTICAL INTERFACE Port pin used Enable bit in OIER PA0 and PA1 PA2 and PA3 PA4 and PA5 PA6 and PA7 OPTICAL INTERFACE OIE0 OIE1 OIE2 OIE3 MOTOROLA 11-1 ...
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... GENERAL RELEASE SPECIFICATION PAx PA(x+1) Figure 11-1. A pair of Optical Coupler Interface VREF2 VREF1 VREF0 OIE2 OIE3 OIE1 OIE0 OPTI_EN PAx OPTICAL INTERFACE Figure 11-2. Optical Interface Comparator MOTOROLA 11-2 November 5, 1998 Output Buffer 0 MUX Optical 1 Interface select select Optical 1 Interface MUX ...
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... Table 11-2. Optical Interface Reference Voltage Selection VREF2 VREF1 MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION BIT 6 BIT 5 BIT 4 BIT 3 VREF2 VREF1 VREF0 VREF0 Reference Voltage (mV OPTICAL INTERFACE BIT 2 BIT 1 BIT 0 OIE3 OIE2 OIE1 OIE0 300 430 560 690 820 950 1080 1210 MOTOROLA 0 11-3 ...
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... TCMPE — Timer Input Capture Comparator Enable This bit is used to enable the comparator in the 16-bit timer input capture circuit. Please refer to 16-BIT TIMER section Timer input capture comparator is selected Timer input capture comparator schmitt trigger is selected. MOTOROLA 11-4 November 5, 1998 OPTICAL INTERFACE MC68HC05JB3 ...
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... Immediate instructions require no memory address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 12 INSTRUCTION SET INSTRUCTION SET MOTOROLA 12-1 ...
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... When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. ...
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... When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch ...
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... Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator MOTOROLA 12-4 November 5, 1998 Instruction INSTRUCTION SET Mnemonic ADC ADD ...
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... The third byte is the signed offset byte. The CPU finds the conditional branch destination by adding the MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION Instruction Mnemonic INSTRUCTION SET ASL ASR BCLR BSET CLR COM DEC INC LSL LSR NEG ROL ROR TST MOTOROLA 12-5 ...
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... Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine MOTOROLA 12-6 November 5, 1998 Instruction Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS ...
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... Stop CPU Clock and Enable Interrupts MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION Instruction Table 12-5. Control Instructions Instruction INSTRUCTION SET Mnemonic BCLR BRCLR BRSET BSET Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT MOTOROLA 12-7 ...
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... ASRA ASRX Arithmetic Shift Right ASR opr ,X ASR ,X Branch if Carry Bit BCC rel Clear BCLR n opr Clear Bit n Branch if Carry Bit BCS rel Set (Same as BLO) BEQ rel Branch if Equal MOTOROLA 12-8 November 5, 1998 Effect on Description (A) + (M) + (C) — A (A) + (M) — A (A) (M) — ...
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... CCR REL REL REL REL REL REL IMM DIR EXT — IX2 IX1 REL REL REL REL REL REL REL REL DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 DIR (b0 DIR (b1) 02 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 REL MOTOROLA 12-9 ...
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... DECX Decrement Byte DEC opr ,X DEC ,X EOR # opr EOR opr EXCLUSIVE OR EOR opr Accumulator with EOR opr ,X Memory Byte EOR opr ,X EOR ,X MOTOROLA 12-10 November 5, 1998 Effect on Description — — — — — PC (PC push (PCL) SP (SP) – 1; push (PCH) — — — — — ...
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... FC 2 DIR EXT IX2 IX1 IMM DIR EXT — IX2 IX1 IMM DIR EXT — IX2 IX1 DIR INH 48 3 INH 58 3 IX1 DIR INH 44 3 INH 54 3 IX1 INH 42 11 DIR INH 40 3 INH 50 3 IX1 INH 9D 2 MOTOROLA 12-11 ...
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... Store Accumulator in STA opr ,X Memory STA opr ,X STA ,X Stop Oscillator and STOP Enable IRQ Pin STX opr STX opr Store Index STX opr ,X Register In Memory STX opr ,X STX ,X MOTOROLA 12-12 November 5, 1998 Effect on Description (A) (M) — — C — — — — ...
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... Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two’s complement) Loaded with If Concatenated with Set or cleared Not affected MOTOROLA 12- ...
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Bit Manipulation Branch DIR DIR REL DIR INH MSB LSB BRSET0 BSET0 BRA NEG NEGA 3 DIR 2 DIR 2 REL 2 DIR BRCLR0 BCLR0 BRN ...
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... MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION SECTION 13 Symbol and stg NOTE and V within the range from V OUT Symbol ELECTRICAL SPECIFICATIONS Value Unit –0 – 0 +150 +70 C –40 to +85 C –65 to +150 OUT Value Unit C/W C/W C/W C/W MOTOROLA 13-1 . ...
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... Input Pull-down Current PA0-7, PB0, PB4-7, PC0-3 (with individual pull-down activated) Input Current RESET, IRQ, OSC1 Capacitance Ports (as Input or Output) RESET, IRQ, OSC1, OSC2 Crystal/Ceramic Resonator Oscillator Mode Internal Resistor OSC1 to OSC2 MOTOROLA 13-2 November 5, 1998 = +70 C, unless otherwise noted) A Symbol ...
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... Min I 0V<Vin<3.3V – |(D+)–(D–)| 0.2 DI Includes 0.8 CM range 15k 2.8 OH GND V I =200 A 3.0 3.3 L ELECTRICAL SPECIFICATIONS Min Typ Max Unit 3.3 3 6.0 OSC = OSC2 –0.2 VDC Typ Max Unit +10 2.5 2.0 0.3 3.6 3.3 3.6 MOTOROLA 13-3 ...
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... Measured from 10% to 90% of the data signal. 5. The rising and falling edges should be smooth transitions (monotonic). 6. Timing differences between the differential data signals. 7. Measured at crossover point of differential data signals. 8. Capacitive loading includes 50pF of tester capacitance. MOTOROLA 13-4 November 5, 1998 Conditions Symbol Min (Notes 1,2,3) Notes ...
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... OSC ELECTRICAL SPECIFICATIONS Min Max Units — 6 MHz DC 6 MHz — 3 MHz DC 3 MHz 330 — ns 1.5 — t CYC 0.5 — t CYC note 1 — t CYC 0.5 t — CYC note 1 — t CYC — — TENTATIVELY set at 170 ns t slow f OSC MOTOROLA 13-5 ...
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... GENERAL RELEASE SPECIFICATION MOTOROLA 13-6 November 5, 1998 ELECTRICAL SPECIFICATIONS MC68HC05JB3 REV 1 ...
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... F 1.02 1.52 0.040 0.060 G 2.54 BSC 0.100 BSC H 1.65 2.16 0.065 0.085 J 0.20 0.38 0.008 0.015 K 2.92 3.43 0.115 0.135 L 15.24 BSC 0.600 BSC 0.51 1.02 0.020 0.040 MOTOROLA MAX 27.17 6.60 4.57 0.55 1.77 0.38 3. 1.01 14-1 ...
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... 18X K Figure 14-3. 20-Pin SOIC Mechanical Dimensions 14.4 28-PIN SOIC (CASE 751F) - 28X 0.010 (0.25 -T- G 26X Figure 14-4. 28-Pin SOIC Mechanical Dimensions MOTOROLA 14-2 November 5, 1998 P 10X 0.010 (0.25 SEATING –T– PLANE 14X 0.010 (0.25 -B- 14 ...
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... COP watchdog function disabled COP watchdog function enabled. IRQTRIG – IRQ, PA0-PA3 Interrupt Option 1 = Edge-triggered only Edge-and-level-triggered. MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION APPENDIX A MC68HC705JB3 BIT 6 BIT 5 BIT 4 BIT 3 COPEN IRQTRIG PULLREN PAINTEN OSCDLY BIT 2 BIT 1 BIT 0 LVREN MOTOROLA A-1 ...
Page 128
... Bytes $1DFF $1E00 Bootloader ROM 496 Bytes $1FEF $1FF0 User Vectors 16 Bytes $1FFF Figure A-1. MC68HC705JB3 Memory Map MOTOROLA A-2 November 5, 1998 I/O Registers 64 Bytes EPROM Program Control Register Reserved Reserved Reserved Reserved MFT Vector (High Byte) MFT Vector (Low Byte) ...
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... A.5 EPROM PROGRAMMING Programming the on-chip EPROM is achieved by using the Program Control Reg- ister located at address $3E. Please contact Motorola for programming board availability. A.5.1 EPROM Program Control Register (PCR) This register is provided for programming the on-chip EPROM in the MC68HC705JB3. BIT 7 ...
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... The last two steps must be performed with separate CPU writes important to remember that an external programming voltage must be applied to the V pin while programming, but it should be equal operations. Figure A-2 shows the flow required to successfully program the EPROM. MOTOROLA A-4 November 5, 1998 PGMR CAUTION during normal DD ...
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... IRQ/V PP Programming Time per byte MC68HC05JB3 REV 1 November 5, 1998 GENERAL RELEASE SPECIFICATION START ELAT=1 Write EPROM byte PGM=1 Wait 1ms PGM=0 ELAT=0 Write Y additional byte? N END = +70 C, unless otherwise noted) A Symbol Min — EPGM Typ Max Unit — mA — MOTOROLA A-5 ...
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... GENERAL RELEASE SPECIFICATION MOTOROLA A-6 November 5, 1998 MC68HC05JB3 REV 1 ...
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...
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... Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its offi ...