MC14001UBCL Motorola, MC14001UBCL Datasheet
MC14001UBCL
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MC14001UBCL Summary of contents
Page 1
... V out should be constrained to the range V SS Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Unused outputs must be left open. REV 3 1/94 MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 Quad 2-Input NOR Gate Quad 2-Input NAND Gate Dual 4-Input NAND Gate ...
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... MC14011B MC14071B Quad 2–Input OR Gate MC14023B MC14075B Triple 3–Input OR Gate MC14012B MC14072B Dual 4–Input OR Gate MC14068B AND MC14081B Quad 2–Input AND Gate MC14073B Triple 3–Input AND Gate MC14082B Dual 4–Input AND Gate PIN PIN 7 FOR ALL DEVICES MOTOROLA CMOS LOGIC DATA ...
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... MC14072B MC14073B Dual 4–Input OR Gate Triple 3–Input AND Gate OUT OUT OUT MC14081B Quad 2–Input AND Gate OUT A 3 OUT MOTOROLA CMOS LOGIC DATA PIN ASSIGNMENTS MC14011B Quad 2–Input NAND Gate OUT OUT OUT OUT OUT MC14068B 8–Input NAND Gate OUT ...
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... MOTOROLA CMOS LOGIC DATA Unit Unit Vdc Vdc Vdc Vdc mAdc mAdc ...
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... All unused inputs of AND, NAND gates must be connected All unused inputs of OR, NOR gates must be connected Figure 1. Switching Time Test Circuit and Waveforms MOTOROLA CMOS LOGIC DATA B–SERIES GATE SWITCHING TIMES Î Î Î Î Î Î Î Î Î pF Î Î Î Î ...
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... Inverter omitted in MC14001B MC14002B, MC14072B One of Two Gates Shown SAME ABOVE * Inverter omitted in MC14002B MC14001B 12 CIRCUIT SCHEMATIC NOR, OR GATES 10, 11 MC14025B, MC14075B One of Three Gates Shown Inverter omitted in MC14025B * Eight Input Gate SAME ABOVE SAME ABOVE SAME ABOVE MC14078B MOTOROLA CMOS LOGIC DATA ...
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... Inverter omitted in MC14023B MC14068B Eight Input Gate SAME AS 4 ABOVE SAME AS 10 ABOVE 11 SAME AS 12 ABOVE V SS MOTOROLA CMOS LOGIC DATA CIRCUIT SCHEMATIC NAND, AND GATES MC14011B, MC14081B One of Four Gates Shown Inverter omitted in MC14011B MC14012B, MC14082B One of Two Gates Shown SAME ...
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... – – 125 C – 3.0 – 4.0 – 5.0 – 6.0 – 7.0 – 8.0 – 9.0 – 10 Figure – 10 Vdc – – 125 C – 6.0 – 8.0 – 10 – 12 – 14 – 16 – 18 – 20 Figure – 15 Vdc MOTOROLA CMOS LOGIC DATA ...
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... INPUT VOLTAGE (Vdc) Figure 10 Vdc V out (a) Inverting Function MOTOROLA CMOS LOGIC DATA 10 8.0 6.0 4.0 2 2.0 4.0 DC NOISE MARGIN The DC noise margin is defined as the input voltage range from an ideal “1” or “0” input level which does not produce output state change(s) ...
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... C 0.145 0.185 3.69 4.69 D 0.015 0.021 0.38 0.53 F 0.040 0.070 1.02 1.78 G 0.100 BSC 2.54 BSC H 0.052 0.095 1.32 2.41 J 0.008 0.015 0.20 0.38 K 0.115 0.135 2.92 3.43 L 0.300 BSC 7.62 BSC 0.015 0.039 0.39 1.01 MOTOROLA CMOS LOGIC DATA ...
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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...