IDT72403L35D Integrated Device Technology, Inc., IDT72403L35D Datasheet

IDT72403L35D

Manufacturer Part Number

IDT72403L35D

Description

CMOS parallel fifo 64 x 4-bit and 64 x 5-bit

Manufacturer

Integrated Device Technology, Inc.

Datasheet

1.IDT72403L35D.pdf (8 pages)

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FEATURES:

• First-ln/First-Out Dual-Port memory

• 64 x 4 organization (IDT72401/72403)

• 64 x 5 organization (IDT72402/72404)

• RAM-based FIFO with low falI-through time

• Low-power consumption

• Maximum shift rate — 45MHz

• High data output drive capability

• Asynchronous and simultaneous read and write

• Fully expandable by bit width

• Fully expandable by word depth

• IDT72403/72404 have Output Enable pin to enable

• High-speed data communications applications

• High-performance CMOS technology

• Available in CERDIP, plastic DIP and SOIC

• Military product compliant to MlL-STD-883, Class B

• Standard Military Drawing #5962-86846 and

• Industrial temperature range (–40 C to +85 C) is avail-

DESCRIPTION:

performance First-ln/First-Out memories organized 64 words

by 4 bits. The IDT72402 and IDT72404 are asynchronous

high-performance First-ln/First-Out memories organized as

FUNCTIONAL BLOCK DIAGRAM

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

and IDT72404)

— Active: 175mW (typ.)

output data

5962-89523 is listed on this function.

able (plastic packages only)

Integrated Device Technology, Inc.

The IDT72401 and IDT72403 are asynchronous high-

(IDT72402

0-3

CONTROL

MASTER

DATA

RESET

LOGIC

INPUT

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

CMOS PARALLEL FIFO

64 x 4 and 64 x 5

WRITE MULTIPLEXER

READ MULTIPLEXER

WRITE POINTER

READ POINTER

MEMORY

ARRAY

64 words by 5 bits. The IDT72403 and IDT72404 also have an

Output Enable (

at the data input (D

in/first-out basis.

word to be shifted to the output while all other data shifts down

one location in the stack. The Input Ready (IR) signal acts like

a flag to indicate when the input is ready for new data

(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The

IR signal can also be used to cascade multiple devices

together. The Output Ready (OR) signal is a flag to indicate

that the output remains valid data (OR = HIGH) or to indicate

that the FIFO is empty (OR = LOW). The OR can also be used

to cascade multiple devices together.

IR and OR signals to form composite signals.

of one device to the data outputs of the previous device. The

IR pin of the receiving device is connected to the SO pin of the

sending device and the OR pin of the sending device is

connected to the Shift In (SI) pin of the receiving device.

nous allowing the FIFO to be used as a buffer between two

digital machines of widely varying operating frequencies. The

45MHz speed makes these FlFOs ideal for high-speed com-

munication and controller applications.

the latest revision of MIL-STD-883, Class B.

A Shift Out (SO) signal causes the data at the next to last

Width expansion is accomplished by logically ANDing the

Depth expansion is accomplished by tying the data inputs

Reading and writing operations are completely asynchro-

Military grade product is manufactured in compliance with

0-D3, 4

) pin. The FlFOs accept 4-bit or 5-bit data

CONTROL

DATA

OUTPUT

ENABLE

LOGIC

). The stored data stack up on a first-

OUT

OE (IDT72403 and

IDT72404)

0-3

(IDT72402 and

IDT72404)

IDT72401

IDT72402

IDT72403

IDT72404

MAY 1998

2747 drw 01

DSC-2747/7

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IDT72403L35D Summary of contents

Page 1

... IDT72404) MASTER MR RESET The IDT logo is a registered trademark of Integrated Device Technology, Inc. FAST is a trademark of National Semiconductor, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES ©1998 Integrated Device Technology, Inc. For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391. ...

Page 2

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and PIN CONFIGURATIONS IDT72401/IDT72403 (1) NC/ GND 8 PLASTIC DIP (P16-1, order code: ...

Page 3

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and OPERATING CONDITIONS (Commercial 5.0V 10 Symbol Parameter (1) t Shift in HIGH Time SIH t Shift in LOW TIme SIL t Input Data Set-up IDS ...

Page 4

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load CAPACITANCE ( 1.0MHz) A Symbol Parameter ...

Page 5

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and FUNCTIONAL DESCRIPTION These and FIFOs are designed using a dual port RAM architecture as opposed to the traditional shift register approach. This FIFO ...

Page 6

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and ( (1) INPUT DATA NOTES: 1. FIFO is initially full pulse is applied held HIGH soon as IR becomes ...

Page 7

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and (1) DATA OUTPUT NOTE: 1. FIFO initially empty. t MRW IR (1) ( DATA OUTPUT NOTE: 1. Worst case, FIFO initially full. DATA OUT ...

Page 8

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO and COMPOSITE D INPUT 0 READY SHIFT ...

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