MC14559BCL Motorola, MC14559BCL Datasheet

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MC14559BCL

Manufacturer Part Number
MC14559BCL
Description
Successive approximation register
Manufacturer
Motorola
Datasheet
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Successive Approximation
Registers
8–bit registers providing all the digital control and storage necessary for
successive approximation analog–to–digital conversion systems. These
parts differ in only one control input. The Master Reset (MR) on the
MC14549B is required in the cascaded mode when more than 8 bits are
desired. The Feed Forward (FF) of the MC14559B is used for register
shortening where End–of–Conversion (EOC) is required after less than eight
cycles.
conversion, with serial and parallel outputs.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
REV 3
1/94
MAXIMUM RATINGS*
X = Don’t Care t–1 = State at Previous Clock
DC Supply Voltage
Input Voltage, All Inputs
DC Input Current, per Pin
Power Dissipation, per Package†
Operating Temperature Range
Storage Temperature Range
MOTOROLA CMOS LOGIC DATA
SC SC( t–1 ) MR MR( t–1 ) Clock
The MC14549B and MC14559B successive approximation registers are
Applications for the MC14549B and MC14559B include analog–to–digital
Motorola, Inc. 1995
X
X
1
1
1
0
Totally Synchronous Operation
All Outputs Buffered
Single Supply Operation
Serial Output
Retriggerable
Compatible with a Variety of Digital and Analog Systems such as the
MC1408 8–Bit D/A Converter
All Control Inputs Positive–Edge Triggered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads, One Low–Power
Schottky TTL Load or Two HTL Loads Over the Rated Temperature
Range
Chip Complexity: 488 FETs or 122 Equivalent Gates
“P and D/DW” Packages: – 7.0 mW/C From 65 _ C To 125 _ C Ceramic
“L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
X
X
X
X
0
1
X
1
0
0
0
0
Rating
MC14549B
X
X
X
0
1
0
(Voltages referenced to V SS )
None
Reset
Start
Conversion
Start
Conversion
Continue
Conversion
Continue
Previous
Operation
TRUTH TABLES
Action
Symbol
V DD
T stg
V in
P D
T A
I in
– 0.5 to V DD + 0.5
SC SC( t–1 ) EOC Clock
X
X
1
0
0
1
– 55 to + 125
– 65 to + 150
– 0.5 to + 18
Value
500
10
X
X
X
0
1
0
MC14559B
X
0
0
0
1
1
mAdc
Unit
Vdc
Vdc
mW
_ C
_ C
None
Start
Conversion
Continue
Conversion
Continue
Conversion
Retain
Conversion
Result
Start
Conversion
Action
T A = – 55 to 125 C for all packages.
* For MC14549B Pin 10 is MR input.
ORDERING INFORMATION
For MC14559B Pin 10 is FF input.
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
MC14549B
MC14559B
S out
V SS
Q4
Q5
Q6
Q7
PIN ASSIGNMENT
D
C
1
2
3
4
5
6
7
8
MC14549B MC14559B
16
15
14
13
12
10
11
9
DW SUFFIX
CASE 751G
CERAMIC
CASE 620
CASE 648
L SUFFIX
P SUFFIX
PLASTIC
Plastic
Ceramic
SOIC
Q3
V DD
Q2
Q1
Q0
EOC
*
SC
SOIC
1

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MC14559BCL Summary of contents

Page 1

... Start Conversion Continue Conversion Continue Previous Operation X = Don’t Care t–1 = State at Previous Clock REV 3 1/94 MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 Symbol Value Unit V DD – 0 Vdc V in – 0 0.5 Vdc mAdc P D 500 – 125 stg – 150 MC14559B SC SC( t– ...

Page 2

... Adc 5.0 7.5 — — pF 0.005 5.0 — 150 Adc 0.010 10 — 300 0.015 20 — 600 Adc MOTOROLA CMOS LOGIC DATA ...

Page 3

... PLH , t PHL = (0.66 ns/pF PLH , t PHL = (0.5 ns/pF SC Setup Time Clock Pulse Width Pulse Width — Clock Rise and Fall Time Clock Pulse Frequency * The formulas given are for the typical characteristics only. MOTOROLA CMOS LOGIC DATA ( pF Symbol TLH 5 THL 5 ...

Page 4

... INH — Indicates Serial Out is inhibited low. * — ninth–bit of serial information available from 8–bit register. NOTE: Pin MC14549B MC14559B WH(cl) 50 PLH 50 TLH S out NOTE: Pin TIMING DIAGRAM INH WH( 50% t PHL 90% 10% t PLH t THL 50% 90% 10% t TLH Q8* INH MOTOROLA CMOS LOGIC DATA ...

Page 5

... FF allows EOC to activate 4–stage register. ** Cascading using EOC guaranteed; no stable unfunctional state. †Completion of conversion automatically re–initiates cycle in free run mode. MOTOROLA CMOS LOGIC DATA OPERATING CHARACTERISTICS conversion, tie Q1 to FF; the part will respond as shown in the timing diagram less two bit times. Not that Q1 and Q0 will still operate and must be disregarded. For 8– ...

Page 6

... This 12–bit ADC is continuously recycling. The serial as well as the parallel outputs are updated every thirteenth clock pulse. The EOC pulse indicates the completion of C MC14559B DAC Figure 2. Externally Controlled 6–Bit ADC C MC14559B DAC Figure 3. Continuously Cycling 8–Bit ADC S out EOC S out EOC MOTOROLA CMOS LOGIC DATA ...

Page 7

... With these two linear parts it is possible to construct SA– ADCs with an accuracy eight bits, using as the regis- ter one MC14549B or one MC14559B. An additional CMOS block will be necessary to generate the clock frequency. Additional information on successive approximation ADC is found in Motorola Application Note AN–716 out SC ...

Page 8

... C 0.145 0.175 3.69 4.44 D 0.015 0.021 0.39 0.53 F 0.040 0.70 1.02 1.77 G 0.100 BSC 2.54 BSC H 0.050 BSC 1.27 BSC J 0.008 0.015 0.21 0.38 K 0.110 0.130 2.80 3.30 L 0.295 0.305 7.50 7. 0.020 0.040 0.51 1.01 MOTOROLA CMOS LOGIC DATA ...

Page 9

... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...

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